hi,
is there a way to load Tcl Tk 8.5 when writing simvision plugins?
is there a way to load the Tcl Tile package (or other Tcl GUI packages) in simvision?
is there a c++ API for writing plugins (besides the tcl API) where i can use Qt/Gtk/Wx to create the GUI ? a java API for writing plugins?
Hi,
I am trying to run a simulation on my schematic using NC-Verilog in Virtuoso. When I click simuate, I keep getting these errors:
irun: *E,FMUK: The type of the file (/counter_run1/testfixture.template) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds0/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds1/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds2/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds3/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds4/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds5/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds6/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds7/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds8/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds9/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds10/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds11/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds12/netlist) could not be determined.
irun: *E,FMUK: The type of the file (ihnl/cds13/netlist) could not be determined.
Does anyone know how to fix this? Thanks.
Hi,
i am working with imc coverage tool for ip coverage.
certain if-elsif conditions are not covered even if i write various test patterns for it. even if i write all combinations in a testpattern for those specific condition, the tool reports some combinations as uncovered. Help/suggestions awaited!
I have a Testbench with a DUT which has VHDL and Verilog RTL modules. The tb_top is verilog. The test file is a verilog.
From the verilog test, I need to force a signal inside the DUT several hierarchies down.
The signal I need to force is inside a VHDL module. This signal is not available at the top level.
How do I do it?
I am using ncverilog/ncvhdl/irun version of 9.2.
Any suggestions with some simple code example is going to be very helpful.
Thanks,
-Ashfaq Hossain
Hi,
I am facing the below error when i tried to simulate a simple verilog environment,is this the tool setup issue w.r.t my source file or something other,please help me out.
Regards
kaleem.
Hi, I'm a newbie in NC-verilog field.
After launched the simvision, I sent some signals to waveform window from Design Browser window.
Before I quit the simvision, how can I save the signals info in waveform window, so I can load this info next time I run the simulation with simvision, instead of drawing these signals one by one from Design Browser window again.
What's more, I wonder if there's a script way to specify which signals should be sent to waveform window. Then the specified signals will be added to waveform window automatically every time the simvision is launched, just as tcl in Modelsim?
Thanks in advance!
Hi shahein,
this sounds like a VHDL issue and not a tool issue. Please refer to the VHDL LRM (IEEE1076) and refer to default types and precision. This will probably explain the behavior you are seeing and provide information on correct data types to use. Should you find any of the tools are not consistent with the LRM, please file a Service Request so that it can be addressed
thanks,
gh-
I have found some application notes that provide guidance on how to use the Dynamic Load and Reseed Methodology with e/Specman. Is there an application note or other guidance on how to perform Dynamic Loading and Reseeding using a System Verilog UVM environment?
Thank you,
Chris
Hi is there a way to print all the macros? we've got a sim env where macros are defined from command line, verilog and specman files. i am looking for a way to list all of the `define during simulation
thx
dean
Hi everyone,
Is it possible to pass events to a method or TCM in e language? I have a TCM which emits events based on some register settings.
I have five such registers and each register does the same function but on different group. Initially i thought of creating a list of events and pass the index number to the TCM and it can emit the respective event. But i belive e do not support list of events. So i was checking if it is possible to pass events as parameters to the TCM and there is nothing mentioned about this in e ref manual.
Can someone share some information if it is possible or is there any work around? Thanks in advance for your help.
I've generated a netlist for a testcase and get the following error in the irun.log:
Elaborating the design hierarchy:
bias i_bias ( .ibias(ibias[3:0]), .vdd(vdd), .vss(vss), .en(en[0]));
|
ncelab: *E,CUINFI (./netlist.vams,39|41): An interface declaration must be connected to an interface (test_top.i_top).
Analog vdd, vss;
|
ncelab: *E,CUIMBC (./development/SYS_VLOG_ANA_TEST/bias_verilog.sv,42|12): An interface port declaration must be connected (test_top.i_top.i_bias).
bias i_bias ( .ibias(ibias[3:0]), .vdd(vdd), .vss(vss), .en(en[0]));
|
ncelab: *E,CUINFI (./netlist.vams,39|52): An interface declaration must be connected to an interface (test_top.i_top).
Analog vdd, vss;
|
ncelab: *E,CUIMBC (./development/SYS_VLOG_ANA_TEST/bias_verilog.sv,42|17): An interface port declaration must be connected (test_top.i_top.i_bias).
That goes on for a while and there are a number of them. So, the question is how do I connect the port declaration? Here's the file referenced:
import ADMS_signals_pkg::*;
module bias (
vdd,
vss,
en,
ibias
);
`include "parameters.svh"
Analog vdd, vss;
Analog ibias[3:0];
input wire en;
Amps iout[3:0];
integer vdd_ok;
integer vss_ok;
integer supplies_ok;
event started;
// Driver vdd_d = new(vdd);
// Driver vss_d = new(vss);
ISource ibias_src[3:0];
initial begin
foreach (ibias_src[i])
begin
ibias_src[i]=new(ibias[i]);
end
@(en == 1'b1 && supplies_ok == TRUE);
#100 -> started;
end
// Driver ibias_d = new(ibias[1]);
// Driver ibias_d = new(ibias[2]);
// Driver ibias_d = new(ibias[3]);
always @(vdd.changed)
begin
if (vdd.v < VDD_MIN)
vdd_ok = FALSE;
else if (vdd.v > VDD_MAX)
vdd_ok = FALSE;
else
vdd_ok = TRUE;
end
always @(vss.changed)
begin
if (vss.v < VSS_MIN)
vss_ok = FALSE;
else if (vss.v > VSS_MAX)
vss_ok = FALSE;
else
vss_ok = TRUE;
end
always @(vdd_ok, vss_ok)
begin
if (vdd_ok == TRUE && vss_ok == TRUE)
supplies_ok = TRUE;
else
supplies_ok = FALSE;
end
initial iout[0] = -IBIAS_TYP;
initial iout[1] = -IBIAS_TYP;
initial iout[2] = -IBIAS_TYP;
initial iout[3] = -IBIAS_TYP;
always @(started,en)
begin
foreach (ibias_src[i])
if ( en==1'b1 && supplies_ok==TRUE)
ibias_src[i].seti(iout[i]);
else
ibias_src[i].seti(0.0);
end
endmodule // bias
Hi,When I use the Ultrsim tools verification the PLL Clock connect to digiatal module, the analog through the connect module(E2L) ，the output logic ignores some toogle edge,How to Solve this problem?
Hi All,
I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is driven by the master. I would like the interface to split the bus such that one slave is driven by the LSB and the other slave is driven by the MSB of the bus.
I believe the easiest way of doing this is to use modports - a master modport and a different modport for each slave. The interface code would then look something like this (modports are on single lines for compactness):
interface data_bus_if
logic [1:0] data;
modport master (output data);
modport slave0 (input .data_bit(data[0]));
modport slave1 (input .data_bit(data[1]));
endinterface : data_bus_if
I'd imagine this scenario is quite common but Incisive doesn't appear to support modport expressions. How can I implement the interface so that it compiles with Incisive?
Many thanks!
Hi,
I will explain my query with an example.
AddrHigh is a 16-bit address which is enumerated as NORMAL, DEVICE etc.. AddrLow is also a 16-bit address which is enumerated as TIMER, UART etc..
I want to concatenate AddrLow and AddrHigh, and declare bins like below. I don't want to specify binary values instead I want specify bins using enumerated names. Is it possible? If yes, what is the syntax?
a: coverpoint {AddHigh, AddrLow} {
//bins
}
Hi everybody ,
Can anybody please suggest me quickstart tutorial to specman-e . I have knowledge of systemverilog uvm and now i want to shift to specman e. I Have specman 9.2 and above... are there any tutorials provided by cadence with the tools???
Thanks and regs,
Pravin
Hi all,
I'm very new to ASIC world.I have done lec b/w a RTL & a NETLIST.I have used hierarchial comparison for this.There are some un equivalent pointsI have got some few issues and doubts regarding those
1.Two modules were unequivalent because of unequivalent blackbox(that black boxes are done by tool).When I checked the diagnose point,it showed unknown.those black boxes are not the memory libraries even and got same name in both rtl and netlist.How this happens?Why tool blackboxed that instance?Will that un equivalent blackbox cause functional mismatch?How can I resolve those?
2.I had some Abort points,but I resolved those by {analyze abort -compare} command and setting multiplier implementation and making compare effort high.Now no Abort points are there.Were they the correct method to resolve those?
3.I also have 2 modules with un equivalent CUTPOINTS,and when I started searching in internet,I came to know that cuts are made by the tool for combinational feedback loops and those are tool defined and will not be a cause of functional mismatch. Can I neglect those unequivalent CUTPOINTS?
Can anyone help me out solving all these?Since Im doing LEC for the first time I face several problems and doubts.Please do reply.........
Hi,
I have a 1-bit signal whose low or high value needs to compared against a certain time value. For eg. signal x is high for more than 5ns at what places in the waveform. I could not use expressionwindow and simcompare manager to do this. Is there any way?
Regards,
Vijay
