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K-i-t-c-h-e-n-s For Sale Exeter Area UK
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I am checking the code coverage for one of my Module's testbench, but the expression coverage is appearing as "n/a" , why is that so ? there are if-else & assignments in the RTL... how do I enable it ?
I am checking the code coverage for one of my Module's testbench, but the expression coverage is appearing as "n/a" , why is that so ? there are if-else & assignments in the RTL... how do I enable it ?
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[AHB eVC]How to send transfers with no IDLE cycles
Hi,
I want to send multiple SINGLE bursts with no intervals in between. like 2-2-2-2-2-2-2-2...
However, when I use the following source code, I got a couple of IDLE cycles like 2-2-0-2-2-2-0-2-0-2..., and I don't understand why. Can anybody help me?
(I am using non_blocking_write api, so there will be no 1 cycle loss between bursts.)
struct ahb_trans{
trans_type : vr_ahb_burst_kind;
trans_dir : vr_ahb_direction;
trans_size : vr_ahb_transfer_size;
trans_addr : vr_ahb_address;
trans_data : vr_ahb_data;
};
extend vr_ahb_master_seq_kind : [ MY_SEQ ];
extend MY_SEQ vr_ahb_master_seq {
!ahb_trans;
for i from 0 to 10 {
gen ahb_trans;
non_blocking_write( ahb_trans.trans_addr,
{ahb_trans.trans_data},
ahb_trans.trans_type,
ahb_trans.trans_size);
};
};
* MY_SEQ will be used in MAIN sequence.
Appreciate any help.
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[SV] Constraint solver issue
hello
below is a class I use for randomize some settings of a ADC controller RTL.
I got the following error
stop -create -name Randomize -randomize
Created stop Randomize
assert ( gpadc_settings0.randomize(lo_thre,hi_thre)); // with c_hilo_thre);
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ncsim: *W,SVRNDF (./my_task.v,315|41): The randomize method call failed.
Observed simulation time : 22747513300 PS + 0
ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints:
shortint'(men.VBUSOUT ) + shortint'(men.CHPWR ) + shortint'(men.VBUSIN ) + shortint'(men.VSYS ) >= men_num ; (/proj/pm8282d1/wa/stanzani/pm8282d1_des/r1.0.0/digital/top/dig/sim/test_board/tb/gpadc_pkg.sv,761)
ncsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints:
state variables:
men_num (4) [/proj/pm8282d1/wa/stanzani/pm8282d1_des/r1.0.0/digital/top/dig/sim/test_board/tb/gpadc_pkg.sv, 747]
22747513300 PS + 0 (stop Randomize: Randomize failure)
I do not understand where the conflict is. It looks to me than men and *thre are completeely independent variables which are randomized separately but surely there is something I do not understand about the constraint solver operation.
typedef struct packed {
bit M15;
bit M14;
bit M13;
bit TINT; //12
bit IVBUSOUT; //11
bit VBUSOUT; //10
bit PMODE; // 9
bit GPADC0; // 8
bit CHPWR; // 7
bit VSYS; // 6
bit VBATC2; // 5
bit VBATC1; // 4
bit VBATSNSN; // 3
bit VBATSNSP; // 2
bit VBUSIN; // 1
bit M0; // 0 LSB
} t_meas_en_reg;
class cl_gpadc_settings;
rand t_meas_en_reg men;
byte unsigned men_num=4;
randc bit[3:0] slow; // slow down the sampling clock frequency
rand bit [11:0] meas_off;
randc byte unsigned lo_thre[9];
randc byte unsigned hi_thre[9];
rand bit [3:0] stretch; // additional setting time for the acq.phase
constraint c_men {
men.M0==0;
men.M13==0;
men.M14==0;
men.M15==0;
shortint'(men.IVBUSOUT) + shortint'(men.TINT ) + shortint'(men. PMODE ) + shortint'(men.GPADC0 ) +
shortint'(men.VBATC2 ) + shortint'(men.VBATC1) + shortint'(men.VBATSNSN) + shortint'(men.VBATSNSP) +
shortint'(men.VBUSOUT ) + shortint'(men.CHPWR ) + shortint'(men.VBUSIN ) + shortint'(men.VSYS ) >= men_num ;
}
constraint c_hilo_thre
{
foreach(lo_thre[i])
lo_thre[i] inside {[5:64]};
foreach(hi_thre[i])
hi_thre[i] inside {[128:255]};
}
// function new (input shortint unsigned min_meas);
// min_meas_en_num = min_meas;
// endfunction:new
function new ();
endfunction:new
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Explicit wire declaration by Virtuoso netlister
Hi all.
When I generate a verilog netlist out of virtuoso ncverilog netlister I see that implicit net s(those internal to modules) are not esplicitly declared. Is there any way to force the netlister to explicitly declare implicit wires.
When implicit nets are multidimensional the netlister declare them. I think there's a way to force this behavior also for scalar wires.
Please help,
thanks in advance.
- See more at: community.cadence.com/.../36386
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How to generate illegal AHB transactions using eVC
Hi,
I am trying to generate some illegal AHB transactions to test how the DUT behaves.
For example, I generated a WORD transaction, then changed the 4-byte aligned address to one that did not align.
I have turned off the checkers in both the master agent and the slave agent by keeping has_check == FALSE;
However, when running the simulation, I still got a constraint contradiction saying that,
*** Error: Contradiction at time 90000, when generating burst (of type vr_ahb_master_driven_burst)
The test was terminated right after this, so it failed to do the job.
Any ideas how to do this?
Thanks in advance.
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[AHB eVC]Unexpected 1ps delay on BFM
Hi,
Another question on AHB eVC.
For some reason, when the master agent drives the AHB signals (to be specific, HSIZE and HADDR), sometimes there will be a 1ps delay(clock period is 3.75ns).
It may or may not happen depend on the seed used. So confused and by checking the log, I dont see any unexpected delay. The logger said that bfm drives the signal at the rising edge of the clock exactly.
Have anybody encountered the same problem?
Any help or your best guess will be appreciated.
Thanks a lot.
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Including `defines with ncvlog netlisting
All,
This is using IC6.1.7-64b.500.6. I have a mixed-signal hierarchy in which several of the blocks have both schematic and Verilog cellviews. The Verilog cellviews are purely digital representations of analog / mixed-signal circuit behavior. I'm using a file with some define statements to govern this behavior. For example, there is a module that does this:
always @ (posedge in) begin
#(`TIME_RUN_ADC);
out = 1;
end
in which TIME_RUN_ADC is defined elsewhere, in a file that gets included in the digital / ams simulations.
When I modify the code in the Cadence text editor and try to extract connectivity, it warns that the variable is not recognized (*E,NOTDIR). I've tried to edit the hdl.var to include -NOWARN NOTDIR, but then ncvlog reports that this error cannot be surpressed. I've also tried using -INCDIR to the directory that holds a file with the defines, but ncvlog still did not find them. Editing hdl.var to include -DEFINE TIME_RUN_ADC=xx works, but there are many different modeling constants throughout the chip that would produce a long list if defined in this way. Is there a way to pass a list of defines to ncvlog? Thanks in advance!
Best regards,
Caspar
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Exclude a net from block coverage
Hi All,
Incisive coverage pragmas works great to turn off coverage on a certain block of a code.
However I was wondering if we could exclude a group of nets from being covered?
For example, As shown below, I have few nets for power supply checks in a verilogAMS code. These nets are declared as wires. I would like to exclude these nets from block coverage. How do I do it?
Any help would be highly appreciated!
Regards,
Sandeep
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Problem with user define net types resolution functions
Hi all,
I have defined a net in this way:
typedef struct{
real V;
real I;
} EEstruct;
function automatic EEstruct res_EE(input EEstruct driver[]);
foreach(driver[i]) begin
.....
to debug my resolution function I need to know which driver is driving the net. How can I know this information?
what kind of data structure driver is? Is there a name field in the driver element or somthing like that?
Another questione,
In the testbench I assign the net in the following way:
assign mynet = '{1.0,2.0}; // is this correct?
assign mynet2 = '{`wrealZState, `wrealZState};
Are this assignment correct?
Thanks,
Jack
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JasperGold connectivity check
I am trying to check this part of code
always @(posedge clk or negedge rstN) begin
if (!rstN)
last_phase <= 1'b0;
else
last_phase <= sample_grant;
end
In this am trying to check only if condition i.e.., if rstN is 0 for this i wrote connection rule as:
CONNECTION,phase,,JDA:LOW,,last_phase
CONDITION,,rstN,0
LATENCIES,0,0,1,0,0
So after running the app the assertion is getting proven but cover is unreachable
Can any one help me out ?
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JasperGold connectivity check.
I am trying to check the following
always @(posedge clk or negedge rstN) begin
if (!rstN)
last_phase <= 1'b0;
else
last_phase <= sample_grant;
end
In the above code i am trying to check the if condition that is if rstN is 0 for that my rule is like below
CONNECTION,phase,,JDA:LOW,,last_phase
CONDITION,,rstN,0
LATENCIES,0,0,1,0,0
After running the app the assertion is proven but cover is unreachable
Can anyone help me out this.
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[IUS] Code profiling
Hi there
I'm asking how (if?) to perform code profiling: I have a simulation which stops and does not terminate due to excess events generation. Since the design is way too complex I am trying to chase the root cause of this behaviour, with no success so far so I am looking for a way to identify the logic which loops around (async logic?)
thanks much
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Verilog instantiating SystemC (generated using Verilator). irun error: Could not load SystemC model library.
Hello,
We are trying to instantiate SystemC module generated using Verilator tool and simulate using irun.
We have a sample counter DUT and we are running 3 configurations.
(1) Pure Verilog
There is top.v, dut.v and a small piece of code for stimulus in top.v. This is for reference.
(2) dut.v converted manually to SystemC dut.cpp
This compiles and runs fine.
(3) dut. converted using Verilator
This is where we encounter following error. Not sure why this error was not encountered in configuration (2) where we have a SystemC module manually written.
Error:
TOOL: ncsc 13.20-s010
ncsc C++ parameters:
ncsc -COMPILER $CDSROOT/tools/cdsgcc/gcc/4.4/bin/g++
-f ./INCA_libs/irun.lnx86.13.20.nc/ncsc_run/ncsc_obj/ncsc.args
-MANUAL
-CFLAGS "-DNCSC
-I$CDSROOT/tools/systemc/include_pch
-I$CDSROOT/tools/tbsc/include
-I$CDSROOT/tools/vic/include
-I$CDSROOT/tools/methodology/OVM/CDNS-2.1.2/sc/src
-I$CDSROOT/tools/methodology/UVM/CDNS-1.1d/sc/sc
-I$CDSROOT/tools/methodology/UVM/CDNS-1.1d/ml/sc
-I$CDSROOT/tools/systemc/include/cci
-I$CDSROOT/tools/systemc/include/factory
-I$CDSROOT/tools/systemc/include/tlm2
-c
-x c++ -m32 -Wall
-I${VERILATOR_INCDIR}
-DVERILATED
-I$CDSROOT/tools/include
-I$CDSROOT/tools/inca/include"
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
ncelab: *F,SCILDD: Could not load SystemC model library ./INCA_libs/irun.lnx86.13.20.nc/librun (./INCA_libs/irun.lnx86.13.20.nc/librun.so: undefined symbol: _Z8vl_fatalPKciS0_S0_).
irun: *E,ELBERR: Error during elaboration (status 3), exiting.
TOOL: irun 13.20-s010: Exiting on Oct 19, 2016 at 10:33:06 IST (total: 00:00:39)
The irun command we are using is -
$ irun
+define+SYSTEMC
-DVERILATED
top.v
dut.v
-sysc
dut.cpp
-access +rcw
-l log.verilator
-I${VERILATOR_INCDIR}
-L${SYSTEMC_LIBDIR}
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Generate an index to an ungeneratable list of struct
Hi,
How do i generate an index to a list of struct with constraints.
For example i have the following struct and list:
struct se_cte_free_mem_area_s
{
!address_start : u64_t;
!address_end : u64_t;
area_size : u64_t;
...
};
!free_mem_areas : list of se_cte_free_mem_area_s;
and i want to generate on the fly an index to the list with constraint (For example where address_start <= address_x <= address_end)?
Thanks,
Yanir.
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Incisive Enterprise Manager Blank Screen
Hello,
I am running Incisive Enterprise Manager on a tiling window manager (dwm 6.0) and whenever I run vmanager, the second window that comes up (the actual incisive enterprise manager) is always a blank gray screen.
I had seen this before when using dwm to run certain programs, such as Matlab. In those cases, it had to do with the particular window-generating Java program assuming a reparenting window manager (not true for my wm, however). I tried using the wmname utility to tell the JDK that I do not have a reparenting wm, but that didn't work. I also tried setting and exporting _JAVA_AWT_WM_NONREPARENTING set to 1, but this also doesn't seem to work.
So my question is this: is there any other way I can get the program to load up correctly in my environment?
Thanks in advance!
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Generate min/max values on modified bitslice scalar
Hi,
How do i generate min/max values on modified bit slice scalar?
For example i trying to do the following and Specman fail during generation:
"
gen_address(alignment : u64_t) : u64_t is
{
var bits_to_zero : int;
case (alignment)
{
2 : { bits_to_zero = 0; };
4 : { bits_to_zero = 1; };
8 : { bits_to_zero = 2; };
16 : { bits_to_zero = 3; };
32 : { bits_to_zero = 4; };
64 : { bits_to_zero = 5; };
128 : { bits_to_zero = 6; };
256 : { bits_to_zero = 7; };
512 : { bits_to_zero = 8; };
1024: { bits_to_zero = 9; };
2048: { bits_to_zero = 10; };
4096: { bits_to_zero = 11; };
};
gen result keeping
{
it[read_only(bits_to_zero):0] == 0;
soft it[read_only(bits_to_zero)] == select {
40: min;
40: max;
20: others;
};
soft it.la_address[63:32] == select {
40: 0xAAAAAAAA;
40: 0xBBBBBBBB;
20: others;
};
};
"
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Error in UVM code
Hi,
I'm getting the following error when running the UVM code present in the following location. There is a sequence_item example which is present.
www.verificationguide.com/.../uvm-sequence-item.html
When i run it with the following command,
ncvlog -sv -uvmaccess -incdir $UVM_HOME/src mem_seq_item_example.sv
i'm getting the following error.
Can someone suggest why i'm getting the error ? I'm not importing the uvm_pkg in the code coz i've used "-uvmaccess" in the command.
Error I got is :
ncvlog: 14.20-s009: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
class mem_seq_item extends uvm_object;
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ncvlog: *E,SVNOTY (mem_seq_item_example.sv,12|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
Suggestions are very much welcome.
~sree205.
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Optimization in concantination of scalar generation
Is there any performance gain on using the following concatenation:
"
address_upper_bits : uint (bits : 17);
address_lower_bits : uint (bits : 47);
address_upper_bits in [0x0, 0x1FFFF];
temp_address == read_only(%{address_upper_bits,address_lower_bits}); // Optimization
address == read_only(temp_address - base_addr_p).as_a(u64_t);
"
Over:
"
(address + read_only(base_addr_p)).as_a(u64_t) not in illegal_range;
"
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BlackBox RTL/GateLevel
Hello!
I would like to create two black boxes one in RTL and another in GATE LEVEL, it can also be one like black box and the other not, however
the two DUTs have the same instance inside the module which accuses the following error:
ncelab: *E,MUNIT: More than one unit matches 'ABC'
attached is an example
//
//---FILE RTL.sv
module ABC;
initial begin
$display ("RTL FILE");
end
endmodule
//---FILE GATE_LEVEL.v
module ABC;
initial begin
$display ("GATE_LEVEL FILE");
end
endmodule
//--- FILE 3 TB.sv
module tb;
ABC DUT_1();
ABC DUT_2();
endmodule
//**** OBS:
///***********
//************ I want to create two black boxes one in RTL and another in GATE LEVEL,
//************ it can be one like black box and the other not, however
//************ the two DUTs have the same instance inside the module which accuses the following error:
//************ ncelab: *E,MUNIT: More than one unit matches 'ABC':
//************ module designlib.ABC:rtl (VST)
//************ module designlib.ABC:gate (VST).
//
Best regards!
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