In my previous company, when we run regressions, the tests are run in parallel which makes the regression finish faster.
There is an already-made script that do that.
Well, I'm not familiar how did they do that so here in my new employer I'm running regression differently which runs the tests one by one, thus it takes so much time to finish the regression.
So, how do you run all/some the tests of the regression in parallel?
Thanks.
Hi to everyone.
I made my circuit in verilogA with the code and circuit part. The simulation is very slow, so I made the systemverilog model.
Now I would compare the results. In some Cadence slide I saw that this is possible:
These are my results:
My question is: Was the image found in the Cadence slide a result of photoshop or is there a function in virtuoso or simvision to compare two results?
If is there this function, how it work?
Thank you very much
L.F.
hi there
simvision (14.10-s007) does not shows up in the hierarchy browser the following output port
output byte data[ 3:0]
i think the byte is considered as a logic [7:0] data type underneath
btw I cannot find a way to see this port in the waveform window ...
strangely output byte [ 3:0] data does not compile (packed arrays of byte are not legal?)
plz. help
thanks much
Dear everyone,
I am pretty new using SimVision and I would be interested in how the uvm_info function is generating hyperlinks for the file and time!
Could anyone please give me some information about how I can make this work with SystemVerilog's $display() function in the same way?
$display("Time: ", $time," | Line: ", `__LINE__," | File: ", `__FILE__); gives me already the correct output, but I'd like to make this output clickable so I can directly see it in source browser and in waveform!
Just want to understand how these hyperlinks work!
Many thanks in advance, really appreciate your help,
René
Hi all,
In simvision, given an assertion, is there a way to get all the timestamps when the assertion was hit?
Thanks.
When I add the -xprop option, a license issue suddenly appears. It says unable to checkout license.
But when I remove this, I'm able to run simulation. Is there an issue with it or am I doing it incorrectly.
The command I used is below:
irun \
-clean \
-xprop F \
-input dump.tcl \
-access rwc \
try_init.sv
Kindly check what is wrong with this.
Thank you.
Regards,
Reuben
Hi everyone,
I finally finish the model of my circuit in System Verilog. There are digital parts and analog parts, it's composed by 15 .sv file and one testbench. Now I would know if is possible to create a library of my model with this files. That means create a unique file, easy to edit, with the possibility of edit the parameter. I don't care if isn't a unique file, the important thing is create the library
Thank you very much for the future answers...
Hi,
Does Cadence have such tool that can trace where x propagation originates?
Thanks.
Regards,
Reuben
Hello, What are the fewest commands to add all signals in design to waveform viewer? Thanks, SysTom
Hello everyone,
I am using a basic UVM Layered Sequences example which is also introduced here:
https://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_guidelines/layering/
My problem is that when I expand the "Monitor" (b2amon/c2bmon) and the variables, the Simulation, which lasts for only 600 ns, becomes pretty unuseful, because I can hardly zoom in and out or move back and forth in time without lags causing me to wait several seconds until the waveform is updated.
Right now I have just like 4 variables and short simulation time, so probably if I add more variables and increase the simulation this effect would cause the whole simulation to be useless, if I can't move around inside the waveform!
Has anyone of you already expierenced similar issues and might want to help me solving this? I really don't know what's the problem with that?!
Would really appreciate your support!
Thanks a lot in advance,
René
I figured out what FUNTSK is but I could not find any canonical list of *Errors and *Warnings for ncsim - do it exist?
Thanks, Tom
Hey everyone,
Does anyone have a good experience with the instantiation of different cells in the same verilogams file?
I'm building a testbench and want to instantiate two instances that have the same name but exist in different libraries, one is schematic and the other one is veriloga.
What I did is the following:
cell1
(*
integer library_binding = "Lib1";
integer view_binding = "veriloga";
*) dutvams (
.x(dutvams_x),
.y(dutvams_y),
.z(dutvams_z)
);
cell2
(*
integer library_binding = "Lib2";
integer view_binding = "schematic";
*) dutsch (
.x(dutsch _x),
.y(dutsch _y),
.z(dutsch _z)
);
I'm also including the path to the veriloga model at the beginning of the verilogams file.
What happens is that when it compiles, it ignores the attributes in between the asterisks completely no matter what I'm tossing in, would only generate syntax errors if it's wrong and generates two schematic instances for Lib2.
When I change the name of the veriloga cell to a different name than the one for the schematic, it works properly.
I'm using virtuoso IC6.1.6.500
I don't know what I'm missing here! Any help would be appreciated, thanks :)
I see the following options for SystemVerilog in irun/ncsim/ncvlog. Why are there two options for SV 2005 and 2009.
What option to use for the latest SystemVerilog 2012(IEEE 1800-2012 SystemVerilog) standard?
-SV -- Enable SystemVerilog features
-SYSV05 -- Enable SystemVerilog features with only SV-2005 and earlier keywords
-SYSV09 -- Enable SystemVerilog features with only SV-2009 and earlier keywords
-SYSV2005 -- Enable SystemVerilog features with only SV-2005 and earlier keywords
-SYSV2009 -- Enable SystemVerilog features with only SV-2009 and earlier keywords
Hi,
I've about 400 test cases to merge all the individual coverage data bases to one output file with use of IMC. I've found the following error during merging process;
merge mipi_base_test*/scope/mipi_base_test -out final -metrics all -initial_model union_all -message 1
merge: too many arguments
merge: usage: merge [-AeEpqxX3] [-L lab [-L lab [-L lab]]] file1 file2 file3
merge aborted
even i tried giving all the individual test names but still giving the above error.
Can any one suggest me to merge all the 400 test cases?(for my case).
regards,
mahee
Hi,
I've about 400 test cases to merge all the individual coverage data bases to one output file with use of IMC. I'm using below IMC version;
IMC(64): 14.10-s011: (c) Copyright 1995-2014 Cadence Design Systems Inc.
I've found the following error during merging process in BATCH MODE;
mydir> imc -batch
imc>merge mipi_base_test*/scope/mipi_base_test -out final -metrics all -initial_model union_all -message 1
imc>merge: too many arguments
imc>merge: usage: merge [-AeEpqxX3] [-L lab [-L lab [-L lab]]] file1 file2 file3
imc>merge aborted
even i tried giving all the individual test names but still giving the above error.
Can any one suggest me to merge all the 400 test cases?(for my case).
regards,
mahee
I try priniting a SimVision Waveform into a .ps (via File->Print Window...), but whenever i do it i get a corrupted file. I tried open it with various tools. They all say "corrupted file" or just show a list of my probes without the waveform on the right.
Is there some kind of trick to make this thing work at all? Any other suggestions to get my waveform as PDF or PNG/BMP file?
I can not send it to a pdf print device, since i remote access SimVision from another computer.
There has to be a possibility.
Hi all,
I am facing a problem when I am trying to simulate verilog code along with analog blocks using the AMS simulator. This is how the story goes:
Initially, with IUS-8.2 installed I was able to simulate simple AMS designs. However, in other AMS designs I was getting an undefined error, which was prompting me to contact Cadence. After searching online, I figured out this had to do with IUS version which was too outdated. Therefore, I asked the sys admin to install INCISIVE-15.20.008. With this package, for the same design I was not able to compile 4 modules from connectLib. For example, for one of the modules I am getting the following error:
ncvlog: *E,NOTSTT (/proj/cad/cadence/incisive-15.20.008.lnx86/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ER_bidir/module/verilog.vams,118|15): expecting a statement [9(IEEE)].
I went back to IUS, by including (softinclude) the appropriate cds.lib file (for IUS) in my cds.lib file. However, when I am trying to simulate the design that I was initially able to simulate with IUS, i.e. before installing INCISIVE, now I get an error displaying:
ncsim: *E,MSSYSTF (/proj/cad/cadence/incisive-15.20.008.lnx86/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2E_2/module/verilog.vams,110|18): User Defined system task or function registered during elaboration and used within the simulation has not been registered during simulation.
It seems that ncsim is trying to compile a module from the INCISIVE installation. Do you have any ideas on how can this be possible?
I double checked that ncsim runs from IUS and not INCISIVE path:
which ncsim
/proj/cad/cadence/ius-8.2.lnx86/tools/bin/ncsim
Let me notice that my configuration is:
IC6.1.5-64b.500.14
MMSIM 13.11
Thank you,
George
Hi,
I recently started using the amsDmv tool to compare results from two different cell views. I was trying to open amsDmv from command line using the command "amsDmv" in the UNIX terminal, however I get the error "command not found." I tried invoking the command from my cds directory and from the path in which my dmv setup was located (although that path should not be necessary). Can you please help me out in finding what the problem could be?
Hi,
I used the amsDmv to compare ADE-XL results for two different config views, and after the completion of the simulation, I observe that the measured results field says "No valid measured results found" when I check the box next to "Validate Measured Results" although the waveform signals field shows a pass or fail. What could be a possible reason for this?
Thanks,
Sampoorna
How to model an simple resistor in SV ?
This is what i have at this moment:
module res_RNM(P,N);
import EE_pkg::*;
inout EEnet P,N;
parameter res=1.0;
.....
endmodule