In an attempt to further my knowledge about Cadence and it's great tools I am seeking help form the community to find out where exactly the name SPECTRE comes from.
A bit of research on the web gives great description of what the tool is for as well as the creators names, Ken Kundert and Jacob White.
Apart from these informations I am still searching where the name comes from.
Any idea ?
Thanks for your help
Hi,
I have reference model of design implemented in my scoreboard.
Now for functional coverage how should I utilise this reference design from scoreboard?
Or Do I need to code same reference design inside coverage model also?
Hi,
I am trying to get a handle on what features of SV 2009 are unsupported.
As an example, I was trying to use the $inferred_clock and $inferred_disable keywords, and getting compilation errors.
Can someone point me to the relevant information?
Thanks,
Steven
I have an issue with ld during the linking process in SystemC environment.
I would like to know if someone knows any workaround or idea to solve this issue!? Thank you.
OS: Ubuntu 16.04 and 16.10
The ncsc_env_check output is (only relevant information):
ncsc_env_check: 15.10-p001: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
There is no native option on linux, switching to gnu.
64-bit environment variable detected, switching to 64-bit mode
INFO: You are using an older make version
[SOME LINES WERE REMOVED]
------------------------------------------------------------
- Performing compiler version check
------------------------------------------------------------
INFO: Your gnu C++ 4.4 compiler is supported
------------------------------------------------------------
- Performing linker/assembler version check
------------------------------------------------------------
INFO: GNU LD version: GNU ld (GNU Binutils) 2.20
INFO: Assembler: <NOT GNU ASSEMBLER>
WARNING: [AS] Assembler version not supported, looking for version (2.16.1|2.17.50|2.18)
[SOME LINES WERE REMOVED]
------------------------------------------------------------
- Performing OS version check
------------------------------------------------------------
ERROR: Your linux OS version is NOT supported: 4.4.0-59-generic
------------------------------------------------------------
- Showing environment data
------------------------------------------------------------
The sanity of your environment is being tested with the following
environment setup
CXX = /soft64/cadence/ferramentas/INCISIVE151/tools/cdsgcc/gcc/4.4/bin/g++
CXX Version = 4.4
CC = gcc
CC Version = 4.4.5
LD = /soft64/cadence/ferramentas/INCISIVE151/tools.lnx86/cdsgcc/gcc/4.4/bin/ld
Perl Directory = /usr/bin
Perl = perl version 5,
Make Directory = /usr/bin
Make = GNU make v4.1
Assembler Directory = /soft64/cadence/ferramentas/INCISIVE151/tools.lnx86/cdsgcc/gcc/4.4/install/bin/as
Assembler = <NOT GNU ASSEMBLER>
CDSROOT = /soft64/cadence/ferramentas/INCISIVE151
NCSC Version = 15.10-p001
NC-Verilog Version = 15.10-p001
NC-VHDL Version = 15.10-p001
[SOME LINES WERE REMOVED]
ncsc_env_check found a total of 14 errors.
---------------------------------------------------------------------
For example, the log from the hello_world_sc is:
» cat ncsc_run.log
TOOL: ncsc_run(64) 15.10-p001: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
ncsc_run \
-64BIT \
test.cpp \
-dynamic \
-top sc_main \
-gnu \
-64BIT
$CDSROOT = /soft64/cadence/ferramentas/INCISIVE151
$TESTDIR = /home/leco/Dropbox/ultrawideband-luis-moreira/uwb-tx-ctrl/ams_sim/envtest/hello_world_sc
TOOL: ncsc(64) 15.10-p001
ncsc C++ parameters:
ncsc -COMPILER $CDSROOT/tools/cdsgcc/gcc/4.4/bin/g++
-f INCA_libs/ncsc_obj/ncsc.args
-MANUAL
-CFLAGS "-DNCSC
-I$CDSROOT/tools/systemc/include_pch
-I$CDSROOT/tools/tbsc/include
-I$CDSROOT/tools/vic/include
-I$CDSROOT/tools/methodology/OVM/CDNS-2.1.2/sc/src
-I$CDSROOT/tools/methodology/UVM/CDNS-1.1d/sc/sc
-I$CDSROOT/tools/methodology/UVM/CDNS-1.1d/ml/sc
-I$CDSROOT/tools/systemc/include/cci
-I$CDSROOT/tools/systemc/include/factory
-I$CDSROOT/tools/systemc/include/tlm2
-fPIC
-c
-x c++ -Wall"
ncsc: compiling $TESTDIR/test.cpp
building library ncsc_model.so
ld: BFD (GNU Binutils) 2.20 internal error, aborting at ../../binutils-2.20/bfd/reloc.c line 446 in bfd_get_reloc_size
ld: Please report this bug.
collect2: ld returned 1 exit status
INCA_libs/Makefile.ncsc:411: recipe for target 'libncsc_model.so' failed
make: *** [libncsc_model.so] Error 1
ncsc_run: *E,TBBLDF: Failed to build test library
./libncsc_model.so
Hello,
This is probably a lame question.
I am trying to develop some Verification Infrastructure in Specman and I am using a local copy of the Specman e Language reference manual which keeps referring to the "Specman Intehrators Guide".
I tried looking for it in the cadence forums but I couldn't find it.
Can someone please give me some information on how to access it?
Thanks.
Hi,
I'm looking for knowing on how to get the information on how much time consumed during compile,elaboration and simulation phases for any test in IRUN.
If there is any switch please provide some suggestions?
Regards,
Mahesh
Hi all,
I am first time using dpi-c functions in my sv code.When I am trying to call dpi-c functions within sv code using irun command(irun -sv test_c.c test.sv).I have tried ncverilog,ncelab,ncsim also but I m getting same like this error,
make: *** [INCA_libs/irun.lnx86.15.10.nc/ncsc_run/ncsc_obj/test_c_0.o] Error 1
In file included from /usr/include/features.h:385,
from /usr/include/stdio.h:28,
from $TESTDIR/test_c.c:1:
/usr/include/gnu/stubs.h:7:27: error: gnu/stubs-32.h: No such file or directory
ncsc_run: *E,TBBLDF: Failed to generate object ./INCA_libs/irun.lnx86.15.10.nc/ncsc_run/ncsc_obj/test_c_0.o
irun: *E,CCERR: Error during cc compilation (status 1), exiting.
Please can anyone help me to know why this error is coming and what wrong I m doing. And can anyone tell me what are the commands and step by step process to run this two files.
Below is my C and SV code :
//sv code
1>
module main;
import "DPI-C" function void hello();
initial
begin
print();
end
endmodule
2>
//c code
#include <stdio.h>
void hello() {
printf("hello from c");
}
thanks,
JAY
Hi ,
I came to know that there is a way to enable some uvm debug options in simvision.
Can someone let me know what are the switches that needs to be enabled for this.
Thanks,
DN
my vpi_iterate cannot access internal signals but the ports. Please help. Cadence Incisive version is 15.20.017.
I have following module (in SystemVerilog):
module my_block (
input logic a,
input logic b,
input logic c,
output logic z
);
logic intermediate_signal;
assign intermediate_signal = a & b;
assign z = intermediate_signal & c;
endmodule
I have written a VPI routine to grab all the signals in the block above:
#include <sv_vpi_user.h>
#define NULL 0
int dut_dump (char *str) {
vpiHandle handle_scope_iterator;
vpiHandle handle_scope_object;
s_vpi_value object_value;
vpi_printf ("Scope: %s\n", str);
object_value.format = vpiBinStrVal;
handle_scope_iterator = vpi_iterate(vpiNet, vpi_handle_by_name(str, NULL));
while (handle_scope_object = vpi_scan (handle_scope_iterator)) {
vpi_get_value (handle_scope_object, &object_value);
vpi_printf ("net: %s, value %s\n", vpi_get_str(vpiName, handle_scope_object), object_value.value.str);
}
return (0);
}
When I instantiate the block my_block in a testbench and call the dut_dump in the testbench,
module tb ();
...
my_block dut (...);
...
initial begin
....
dut_dump("tb.dut");
...
end
endmodule
Simulation gives following:
ncsim> run
Scope: tb.dut
net: a, value 1
net: b, value 1
net: c, value 1
Memory Usage - 29.3M program + 25.1M data = 54.4M total
It does not iterate the internal signal intermediate_signal.
Subject explains.
During simulaton runtime, there are three ways to read values of signals:
Advantages in terms of speed/performance
Disadvantages
Based on the assumptions above, accessing objects through API (PLI/VPI/DPI) is much faster.
Can anybody elaborate this?
Is it possible to redirect the output of a system task, such as stacktrace, to a string in SystemVerilog?
Hi,
imc does not work on my computer but it work on other computers.
On my computer, lmstat -a:
Users of Affirma_sim_analysis_env: (Total of 2 licenses issued; Total of 0 licenses in use)
Users of Incisive_Desktop_Manager: (Total of 1 license issued; Total of 0 licenses in use)
Users of Incisive_Enterprise_Simulator: (Total of 1 license issued; Total of 0 licenses in use)
Users of Incisive_HDL_Simulator: (Total of 1 license issued; Total of 0 licenses in use)
Users of Incisive_P2C_Methodology: (Total of 1 license issued; Total of 0 licenses in use)
Users of Incisive_Specman_interactive: (Total of 1 license issued; Total of 0 licenses in use)
Users of Incisive_Verif_Environ: (Total of 1 license issued; Total of 0 licenses in use)
Users of VERILOG-XL: (Total of 2 licenses issued; Total of 0 licenses in use)
Users of CaptureCIS: (Total of 2 licenses issued; Total of 1 license in use)
It seems to be something wring with imc, I can run simulation and everything else, but imc wont run. and the licenses are unused.
Any suggestions?
Hi All,
anybody has experience with mapping tests to vPlan in vsif file?
I am using the vManager Client (15.20.s010)! In the vsif file I use the attribute vplan_ref to map a test to a TC item in the vPlan. It looks like below:
test my_test {make_args: "cpu=ON"; sv_seed: random; count: 4; vplan_ref: DOORS_A.SysTS.A_TS_Vplan_Export/A.SysTS-105/A.SysTS-106/A.SysTS-633/A.SysTS-107;};
When the regression is finished, I load the vPlan in GUI (Analysis part)! But the test is not mapped? the configuration file for coverage has below commands:
select_coverage -all
set_com -log set_com.log
select_functional -imm_asrt_class_package
and in the session log file I see the below attribute is set by vManager
BRUN_VPLAN_REF="DOORS_A.A_TS_Vplan_Export/A.SysTS-105/A.SysTS-106/A.SysTS-633/A.SysTS-107"; export BRUN_VPLAN_REF
Appreciate your comments!
Hi,
One of my Specman tests hangs in simulation because one of the component units that raised Objection did not drop it correctly.
I was able to find out approximately which instance did that using *get_objection_total/get_objection_counter*.
Although it would be more helpful if I can find where exactly the objection that is not getting dropped was raised in the first place.
Would appreciate any tips that would enable debug.
While trying to model combinational delay in systemverilog the following was observed.
The below code didn't work
assign #(50ps) b = a;
b was always x state.
But the below code works
parameter real del = 50ps;
assign #(del) b = a;
I feel this is a bug in irun.
File: systemverilog
irun argument -TIMESCALE 1s/1ps
Version irun: 15.20-s008
From the ncvlog.log I see
Using implicit TMP libraries; associated with library worklib
Generating native compiled code:
... ...
thereafter a library directory named inca.<my_lib> was built under the path specified by -nclibdirpath.
My question is how does irun know which source files should be referred to compile to an implicit library?
Thanks in advance！
Hello,
I'm running into a very frustrating issue/bug w/ the waveform viewer in Simvision where the waveform display formatting is not always saved to the svcf file when the "save command script" command is used.
Under the advanced option box I make sure to check the preferences box to save waveform formatting but when I open the .svcf file and view it, the -color and -namecolor fields are not always saved.
The problem does not happen consistently and it does not do it for all the waveforms in the viewer but when it does it is very difficult to get the tool not to keep doing it. Shutting the tool down and restarting does not help. I feel like there is some other option or something I have enabled that prevents the formatting save for certain signals but I can't figure it out and I'm tired of formatting my signals the way I need to only to have the formatting work lost when the script is saved.
Any help would be greatly appreciated.
thanks
If I create a variable in a for-loop:
for(int i=0;i<N;i++) begin...
It creates and unnamed block. If you $display("%m") in the block it is called "...unmblkX" where is an integer.
If I try to name the block (as allowed in Modelsim)
for(int i=0;i<N;i++) begin : my_block...
The behavior does not change. How can I name an unnamed block?
Hi,
here is my simulation log excerpt:
ncsim> uvm_config_db -trace on
ncsim: *E,CLNAIA: Cannot call system tasks/functions while analog engine is interactive.
while executing
"call tcl_uvm_config_db 1 [cdns_get_on_off_mapping $v5] "
("-trace" arm line 1)
invoked from within
"switch -regexp -- $args {
"-dump\\s+-audit" { call tcl_uvm_config_db 0 1 }
"-dump" { call tcl_uvm_config_db 0 0 }
"-trace" { cal..."
(procedure "uvm_config_db" line 10)
invoked from within
"uvm_config_db -trace on "
ncsim>
What actually does it mean? I'm using the ultrasim solver.
Hi all
Is there a way to use the value of string variable in systemverilog. I have a text file with the pin name and the value to be driven to that pin, on each line.
There are around 50 pins. The name of the pin declared in the interface and the text file are same. I want to read the pin name and value from text file into a string and integer.
Then use the string to refer the signal in interface and drive the value to it. The code i want to use is roughly as show below.
The interface vif has pins pinabc and pinbcd declared in it. obviously here when i use vif.pin the tool is searching for a pin with name "pin" in interface. Is there a way to get
the value of the string pin.
----------------file.txt-------------------------
pinabc 20
pinbcd 30
---------------sv code----------------------------------
interger FILE,pin_val;
string line,pin;
FILE = $fopen("./file.txt","r");
while ($fgets(line,FILE)) begin
void'($sscanf(line,"%s %d\n",pin,pin_val));
vif.pin = pin_val;
end