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uvm help needed

June 7, 2012, 7:03 am
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 I am a newbee for uvm. Looking for some understaning on using uvm_tes/uvm_env  under module.

IUS allows me using uvm_env under module but not uvm_test or uvm-agent ,  throwing below error  -

" class my_test extends uvm_test;
                               |
ncvlog: *E,FAABP1 (my_tb.sv,1|31): task, function, or assertion instance does not specify all required formal arguments [10.2.2][10.3(IEEE)]."

Follwing is the code - 

module top;

class my_env extends uvm_env; //works fine

//class my_test extends uvm_test; // Gives error

// class field,function

endclass

endmodule

 

What should be the reason?

thanks

joys

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Elaboration error in SVA binding file

June 7, 2012, 4:13 am
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Hi,

While running the testcase with IUS 11.10.002, I am getting following error fo SVA binding file.

 ncelab: *E,NOBNDT: Bind target module not found

 Any clue on resolving this error?

 

Thanks,

Pinakin

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Help needed on temporal expressions with detach

June 7, 2012, 11:59 pm
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Hi everyone

     I am having trouble in writing a temporal expression using detach construct in e langauge. Any help is greatly appreciated.

    There are two events A and B in my environment. everytime B event happens A should have happened 0~3 clocks earlier.

    My temporal expression looks like below.

    expect @B => detach({@A;~[..3]})@clk else dut_error("B event error");

    In my simulation event B happens a total of 4 times. But the dut error is issued only once i.e. for the very first B event.

    I am wondering why the error is not issued for 2nd, 3rd and 4th events of B.

   I am using specman 10.2 version.

  - regards

    Jayachandra

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forcing the creation of a vcd file

June 15, 2012, 2:44 am
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Hello,

How do I instruct simvision to force the creation of a vcd file?

I am trying to create tcl script to dump signals into a vcd file and then immediately post-process this very vcd.

These are the two lines I want to run in sequence from a ncsim tcl script : 

simvision -submit "database export $my_signals -format vcd -name my_vcd.vcd"

file copy my_vcd.vcd ${my_dir}/myvcd.vcd

The problem that I am experiencing is that simvision seems to postpone the creation of the vcd file. Therefore, at the moment the second line is executed the vcd file is not yet available.

I get the following error:

ncsim> *E,TCLERR: error copying "driver.vcd": no such file or directory

However, if I run the two lines separately (i.e., not in a script) it works.So It seems that I have to force the creation of the vcd, but I don't know how.

I would appreciate your help.

Thanks!

 

 

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Using Dynamically Allocated Memories (PLI)

May 16, 2012, 3:13 am
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Hi 

I am using cadence's pli for dynamically allocated memories. 

for system tasks:

damem_inith - there is one argument which needs file name in the following format:

"bin.dat". 

I would like to replace it by dynamic file name i.e <seed>.dat. So for each random test it will look for filename as <seed> .dat

Is it possible with this system tasks?

 

Thanks!

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Controlling timescale while exporting database

June 18, 2012, 2:24 am
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Hello,

I am trying to export a VCD database using the following command:

simvision -submit "database export $my_signals -format vcd -name my_vcd.vcd"

That works fine but the VCD timescale is not the desired one.

I tried the option "-timeunits ps" but that seems to work only for CSV output format.

I cannot change simvision's time_format as it is a read-only variable.

Does anyone know how to control the timescale whie exporting an existing database into VCD?

thanks

 

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Error : Overflow, divider cannot be zero

June 20, 2012, 8:26 pm
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Hi All,

 

I am using a vr ahb (eVC) and i get this error "Overflow, divider cannot be zero" . I have no clue how to debug this error. Coud anyone please throw some light on thsi error? 

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Loading Coverage Databases

June 21, 2012, 9:11 pm
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Hello,

I am facing some issues while trying to merge coverage data from two tests with different ucd and ucm file names.

The test names are test_1(icc_000.ucm, ic_000.ucd) and test_2(icc_001.ucm, icc_001.ucd).

The execution of command load_test with argument test_* gives me the following error message:

 

"Loading of coverage data ../icc_001.ucd failed due to mismatch in checksum with the loaded model file ../icc_000.ucm"

Can someone help?

 

Thanks in advance,

Jijo

 

 

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Virtual interface in UVM

June 26, 2012, 4:12 am
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HI , 

 

I am wondering who is calling assign_vi virtual function while connecting interface of different members under Agent?

// Assign the virtual interfaces of the agent's children

  function void assign_vi(virtual interface ubus_if vif);

    monitor.vif = vif;

    if (is_active == UVM_ACTIVE) 

      driver.vif = vif;

  endfunction : assign_vi

 

 

thanks

joys 

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Incremental Compilation in Emanager

June 27, 2012, 12:04 am
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Hi All,

 I am using enterprise manager. During regression design files are getting compiled for all the testcases. How to compile it for one file and use it for the rest of the tests.

This incremental compilation is working with "irun" command by default. But it is not working for Emanger. Can any one help me on this.

-Thanks,

Abhinivesh

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How to get the activity power in Simvision

July 24, 2012, 1:21 am
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Dear all,

 

I'm using simvision to analysis activity power.

Here is the command I used:

read_vcd -vcd_module dut -module top -activity_profile -start_time 10000 -end_time 30000 -simvision ../../i303_tb/test/TOP_IO_Power_exper/POWER_EXPER.vcd 

  So, how can I see the activity power in the waveform?

In other words, I want see the active power during the signal changed in waveform.

 

Thanks for the help ^_^. 

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Declaring array of uniquely parameterized classes

July 20, 2012, 9:10 am
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In my SystemVerilog environment, I have an array of a class typefor which I need to customize instantiation parameters for each class in the array.  With all classes the same, I can do

 my_class #(.PARAM1(32), .PARAM2(8)) classes[8];

However, I can't figure out how to customize the PARAM1 and PARAM2 parameters for each specialization.  Is this possible?

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NC_MIRROR help

July 26, 2012, 7:06 pm
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Hi can any one suggest some useful resource for using nc_mirror utility in VHDL. Or even for that matter the syntax of it.

Regards

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Generate random MIN and MAX value from a range of values

August 1, 2012, 5:50 am
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Hi All,

 I would like to know if there is any efficient way to generate a random min and max value from a range of  values?

i have a range VAL1 to VAL2... I need to generate a min_val and max_value within this range such that min_val >=VAL1 and max_val>min_val and max_val<=VAL2 

I am not able to use a variable in the keep constraint.

keep MIN_VAL  in [VAL1.. VAL2]

keep MAX_VAL in [MIN_VAL  .. VAL2] -- NOT POSSIBLE

 So is there any work around without using 'gen' inside while? 

 

Thank you !!!

 

Cheers,

Bharath. 

 

 

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help needed on the use Scemi2.0 Pipe between OVM tb and HDL

August 7, 2012, 5:45 am
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Hello, 

  I want to use the scemi2.0 pipe to connect a ovm TB with a RTL DUT.  In ovm side, I use the ovm_accel_pkg. I made an every simple example, in which a ovm_accel_input_pipe_proxy is used in the tb side and a scemi_input_pipe is used in the DUT side. But when I try to run the compiled snapshot, some mistakes show up like 

     Error: marg_deposit_handle: can't find top_m.dut_i.receive_pipe.fp_elements_count
     Error: marg_value_handle: can't find top_m.dut_i.receive_pipe.fp_read_pending
     Error: top_m.dut_i.receive_pipe.fp_buffer is not a Verilog memory
     Initialization ERROR !!!  port top_m.dut_i.receive_pipe TBA_callback occurred but is not initialized, exiting simulation ...

 

The Makefile I used to compile is : 

  1 c_inc_dir=-I/proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/c \
  2         -I/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba \
  3         -I/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/include \
  4         -I/proj/asic/tools/cadence/incisive/INCISIV_11.10.010/tools.lnx86/include
  5
  6 SRCFILE=top_m.sv \
  7         -incdir .
  8
  9
 10 C_FILE=/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_event.cpp \
 11        /proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_scemi.c \
 12        /proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/lib/libuatba_dc.so
 13
 14
 15 SCEMI_PIPE=/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_event.sv \
 16            /proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_sv.sv \
 17            -incdir /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba \
 18            -v /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba/scemi_pipe.vp
 19 ## -y /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba +libext+.v+.vp+.sv
 20 ##-incdir /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba \
 21
 22 OVM_ACCEL=/proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/sv/ovm_accel_pkg.sv \
 23           -incdir /proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/sv \
 24           /proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/c/ovm_accel_pipe_if.cpp
 25
 26 IRUN_OPT= -DNO_IXCOM -top uatba_event -top top_m  -ovm -sv -dpi -access +rwc -timescale 1ns/1ns +defineall+NO_IXCOM -c
 27
 28 compile:
 29         irun $(IRUN_OPT) $(OVM_ACCEL) $(SRCFILE) $(c_inc_dir) $(C_FILE) $(SCEMI_PIPE)

 

The errors shown above are related to the marg C interface. I guess I did not explicitly specify it. And the 'fp' of 'fp_elements_count' seems to stand for fast pipe. Again, I did not use fast pipe in my example. How can it complain about the fast pipe? I really don't understand.

Is there anyone can tell me where I made mistakes and how to solve it ? Thanks a lot !  I list my codes below. 

 Thanks and best regards, 

Xinwei 

 

 

 

 My code is : 

tb.sv :

  1 import ovm_pkg::*;
  2 import ovm_accel_pkg::*;
  3 `include "ovm_macros.svh"
  4 class data_tran_t extends ovm_object;
  5     reg[7:0] data;
  6     `ovm_object_utils_begin(data_tran_t)
  7         `ovm_field_int(data,OVM_ALL_ON)
  8      `ovm_object_utils_end
  9
 10     function new(string name ="unamed_data_tran_t");
 11         super.new(name);
 12         data=8'hff; // default value for data
 13     endfunction
 14
 15     function void set(int unsigned value);
 16         ovm_report_info(get_type_name(), $sformatf("data is set to  %h",value));
 17         data=value;
 18     endfunction: set
 19 endclass
 20
 21 class tb extends ovm_component;
 22     data_tran_t transaction;
 23     ovm_accel_input_pipe_proxy#(data_tran_t) send_pipe;
 24     `ovm_component_utils_begin(tb)
 25         `ovm_field_object(transaction, OVM_ALL_ON)
 26     `ovm_component_utils_end
 27
 28     function new(string name="unamed_tb", ovm_component parent=null);
 29         super.new(name,parent);
 30         transaction=new("transaction");
 31     endfunction: new
 32
 33     function void build();
 34         super.build();
 35         set_config_string("send_pipe","hdl_path","top_m.dut_i.receive_pipe");
 36         send_pipe=new("send_pipe", this);
 37         send_pipe.set_pipe_name("top_m.dut_i.receive_pipe");
 38
 39     endfunction:build
 40
 41     task run();
 42         transaction.set(20);
 43         send_pipe.put(transaction);
 44     endtask
 45
 46 endclass

 

dut.sv : 

  1 module dut;
  2 scemi_input_pipe#(1,1) receive_pipe();
  3 reg [7:0] rec_data;
  4 integer numRead;
  5 bit eom;
  6    
  7 initial begin
  8     
  9     forever begin
 10         receive_pipe.receive(1,numRead,rec_data,eom);
 11         $display("numRead:  %d", numRead);
 12         $display("recdata:  %h", rec_data);
 13         $display("eom:      %d", eom);
 14     end//forever loop
 15 end//initial
 16 endmodule

 

top_m.sv 

  1 `include "tb.sv"
  2 `include "dut.sv"
  3 module top_m;
  4     tb tb_i=new("tb_i");
  5     dut dut_i();
  6    
  7    initial begin
  8     run_test();
  9    end
 10 endmodule 

 

 

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Using Eplanner with UVM

August 13, 2012, 10:21 am
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I am trying to implement checkers in my UVM environment from my vPlan and to map them in Eplanner. However, in the Eplanner I can only see the checks that I implemented as assertions in interfaces but not the checkers I implemented as assertions in my UVM monitor. Could anyone explain me how should I implement checkers in my UVM monitor in order to see them in Eplanner in order to be able to map them.
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Verification Plan using Eplanner

November 28, 2008, 8:53 am
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 Hi....

 

Can anybody explain me How to map checkers(check that statement) into vplan using eplanner?

 

Thanks! 

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Using interface signals as coverpoint bins

August 20, 2012, 11:46 am
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Hi,

 I have my functional coverage like this:

class mem_cov_grp;

virtual SysRegIntf;

covergroup walks();

level:      coverpoint SysRegIntf.Addr {

                 bins MAX = {31- SysRegIntf.Tag};

                 bins MAX_PLUS_ONE = {31 - SysRegIntf.Tag + 1}; 

              }  

endgroup 

function new (Virtual SysRegIntf);

    this.SysRegIntf = SysRegIntf;

    walks = new(); 

endfunction 

function void sample ();

    walks.sample(); 

endfunction   

endclass 

In this case, bin values are not static and vary depending on Tag bits in the interface. Is this allowed in system verilog?. It compiles well but the bin values are fozen to 31 - 0 = 30 for MAX and 31 - 0 + 1 to 32 to MAX_PLUS_ONE.  

 

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How to filter X -> 0 or X -> 1 from signals for events

August 22, 2012, 12:41 am
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Hi all,

          I am having problem in filtering the changes from x->1 and x->0 on a singal which i use to generate events.

       For example,

            I have a simple port "a" of type in, which is connected to a DUT signal. DUT drives x on the signal "a" for some time initially

 (10ns)   and then drives the value 1. I declared an event as shown below. clk_r is a clock rising event. The first clk_r event is available

  well after signal "a" settles with the value 1.

      event a_e is rise(a$)@clk_r; 

   Because of the change from x->1 on the signal "a", i receive an event on a_e on the first clk_r event.

   Can anyone suggest me how i can filter this unwanted event.

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"INTERNAL EXCEPTION" when ncsim

August 22, 2012, 8:23 pm
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Hi all,

  When I run a project using ncsim, and find the fatal error, which is list as below, I want to know how can I detect the error more deeper.

INTERNAL EXCEPTION
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------

The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncsim 12.10-s003
 
HOSTNAME: sh-c-11.hongkong.cortina.local
 
OPERATING SYSTEM: Linux 2.6.18-238.5.1.el5 #1 SMP Fri Apr 1 18:41:58 EDT 2011 x86_64
 
MESSAGE: missing unilang library
-----------------------------------------------------------------


csi-ncsim - CSI: Cadence Support Investigation, recording details

Code Item: ra (COD_RA)

Intermediate File: root (IF_ROOT)

Verilog Syntax Tree: overlay table (VST_OVERLAY_TABLE) in verilog_package worklib.cvm_pkg:sv (SIG) <0x65123be8>
 
Decompile: cvm_pkg::cvm_vdb

Code Item: stream (COD_STREAM)

Verilog Syntax Tree: overlay table (VST_OVERLAY_TABLE) in verilog_package worklib.cvm_pkg:sv (SIG) <0x65123be8>
 
Decompile: cvm_pkg::cvm_component

Simulator Snap Shot: gd (SSS_GD) in snapshot worklib.ilkn_if:sv (SSS)

Simulator Snap Shot: dynlib (SSS_DYNLIB) in snapshot worklib.ilkn_if:sv (SSS)
Intermediate File: string (IF_STRING) in verilog_package worklib.cvm_pkg:sv (VST)
 Decompile: vmm_str_match
Simulator
Snap Shot: dynpatch (SSS_DYNPATCH) in snapshot worklib.ilkn_if:sv (SSS)
Intermediate File: string (IF_STRING) in snapshot worklib.ilkn_if:sv (SSS)
 Decompile: /auto/tools/cadence/simulation/INCISIV12.10.003/tools/uvm/uvm_lib/uvm_sv/lib/libuvmpli.so

Simulator Snap Shot: root (SSS_ROOT) in snapshot worklib.ilkn_if:sv (SSS)
Internal Code in function: ncmain offset 43

User Code in function: main offset 27

User Code in function: __libc_start_main offset 220

csi-ncsim - CSI: investigation complete took 0.071 secs, send this file to Cadence Support

 Thanks

  Feng

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