Dear Sirs,
could anyone give me an example on how to exclude a bit of an internal bus in the toggle exclude file for ncelab?
For instance, if I use
INSTANCE <pathname>:<bus_name>*
I exclude from the statistics all the bits of the bus, but specifying a single bit, it seems not working
INSTANCE <pathname>:<bus_name>(<bit_number>)
I tried also to escape the parenthesis with
INSTANCE <pathname><bus_name>\(<bit_number>\)
but without success.
Thanks in advance
Sergio
Hello,
I would like to use ncsim's (or simvision's) shell to find out the connectivity of a net.
For example, if I have a wire named clk in my top-level, I would like to get a list of ports that this wire is connected to.
Is this possible? Can you point me how to do that?
Thanks,
Hi
My verification environment is in e language completely. I want to access the events of an unit from top level sequences i build. earlier i used to accesses the events anywhere in the seqeunces using the code shown below.
wait @get_enclosing_unit(top_unit).unit1.unit2.unit3.target_unit.event_name;
Now the same code i am not able to see the events. The sequence keep waiting for the event. But the event is already generated in the target_unit.
I am confused why it is not working now. Any help is greatly appreciated.
- regards
The way I have always probed currents/voltages in ADE was to go to "Outputs>to be plotted>select on schematic" and click every node/pin I need. Now that I've moved to a new system this function does not work. The nodes show up in the outputs window, but when I run a simple single point dc analysis they do not appear.
details:
- I can annotate the node voltages and device operating points on the schematic with no problems
- If I use the calculator to form an equation (i.e. 'VDC("/OUTPUT")', and copy paste it in a row in the output window it will show up as expected, but it takes forever to do this for several nodes/currents.
- This is while using spectre
There seems to be some disconnect between the saved data and the display on the ouputs window. Anyone have a clue?
Thanks.
Hello, I have downloaded the lite version Orcad 16.6, and I have some problem with markers (voltage, current etc.).
When I place marker on the circuit, the marker stays gray and no trace appears in the pspice window. But when I try from "add trace" button in pspice everything is OK. Can you help me with this?
We are using “irun” to run our testcase and we are getting the below warning. Due to this, we are getting a very huge log file (interms of GB). Please could you suggest why we are getting this warning and how to suppress the same?
Built-in relational argument contains a ('U', 'X', 'W', 'Z', '-') in an operand.
ASSERT/WARNING (time 277932200 PS) from package ieee.NUMERIC_STD, this builtin function called from process system.u_chip.u_core.u_cpsTop:u_ethComplex:i_ethTopModule:i_ethManipulationModuleToSerDes:EnetBypassLogicGen(3):i_emmBypassToSerDes:i_loopbackfifo:u_genericTwoPortRam1R1W:projectRamGen:u_projectRamFile:regFileGen:notDualPortRegFileGen:u_genericRegisterFile:regFileB_proc (architecture eth_lib.genericRegisterFile:synth)
Built-in conversion function argument contains ('U', 'X', 'W', 'Z', '-') in an operand (treated as '0').
Does irun 12.20 support multi-core simulation and how to do so .
I had ever use following "-processor" options. It seems that it does not work well.
irun -processor 4
irun -processor 4 -profthread
The version is :
irun: 12.20-s009: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
We are using “irun” to run our testcase and we are getting the below warning. Please could you suggest why we are getting this warning and how to suppress the same?. These assert/warning is related to RAM itseems and we are getting three different mem_error/warning/abnormal transition as list below.
Please could you help us in suppressing these three.
No.1
** MEM_Error: Unknown value occurred in Address.
ASSERT/WARNING (time 707830810500 FS) from process system.u_chip.u_core.u_cpsTop:u_ethComplex:i_ethernity_top.i_switch_top.i_mea_lx.i_if_top.if_core.ihp.st.i_st_dp_wrapper.hash_mem_grp_1[0].m_grp1.m_1w1r_ram.ram_2:VITALBehavior (architecture eth_lib.SZLA40_1024X40X1CM4:behavior)
No.2
** MEM_Warning: Read and Write the same address.
ASSERT/WARNING (time 707830810500 FS) from process system.u_chip.u_core.u_cpsTop:u_ethComplex:i_ethernity_top.i_switch_top.i_mea_lx.i_if_top.if_core.ihp.st.i_st_dp_wrapper.hash_mem_grp_1[0].m_grp1.m_1w1r_ram.ram_1:VITALBehavior (architecture eth_lib.SZLA40_1024X39X1CM4:behavior)
No.3
** MEM_Error: Abnormal transition occurred.
ASSERT/WARNING (time 400 PS) from process system.u_chip.u_core.u_cpsTop:u_ethComplex:i_ethernity_top.i_switch_top.i_mea_lx.i_if_top.if_core.gbe104_rx[0].rx_mac_104_inst.rx_mac_64bit.i_rx_mac.genblk1.i_mem_1024_0.ram:VITALBehavior (architecture eth_lib.SZLA40_512X8X9CM2:behavior)
When I run following command to collect coverage (There are 2000 vsof files)
emanager -coverage -vsof " ./covwork/irun/*/*.vsof " &
I got the Error: vManager Failed: Unexpected error
The reason is Out of memory .
When I run coverage follow. I always get 2 problems:
(1) vManager Failed: Unexpected error ( Out of memory )
(2) If no error, it is very slow and will consume much of memory.
How to solve upper problems.
=================================================================================
Here are more log info:
Reading EManager configuration...
Doing EManager setup...
On-the-fly GC, current size is 2569369600 bytes (including 323404 known free)
Done - total size of reachable data is 79912192 bytes (plus 2467005536 free).
On-the-fly GC, current size is 3124511600 bytes (including 547645728 known free)
Done - total size of reachable data is 83085120 bytes (plus 3022911368 free).
On-the-fly GC, current size is 3198727704 bytes (including 628465380 known free)
Done - total size of reachable data is 85586128 bytes (plus 3093959788 free).
On-the-fly GC, current size is 3254023348 bytes (including 683430808 known free)
Done - total size of reachable data is 87813604 bytes (plus 3147439360 free).
Memory accounting is not enabled. Set the environment variable SPECMAN_MEMORY_ACCOUNTING to enable it
configuration options for: memory
-automatic_gc_settings = STANDARD
-optimal_process_size = 3154116608
-notify_gc_settings = FALSE
-gc_threshold = 1393665248
-gc_increment = 0
-print_msg = TRUE
-print_otf_msg = TRUE
-retain_printed_structs =TRUE
-retain_trace_structs =FALSE
-max_retained_structs = 0
-disable_disk_based_gc = FALSE
-max_size =4273995775
-absolute_max_size = 4294967295
-check_consistency = FALSE
-print_debug_msgs = FALSE
-expand_stack = 0
Please see chapter 'Specman Memory Consumption Is Too High' in the Specman documentation
**** Fatal error - leaving vManager:
Out of memory
vManager failed: Unexpected error
INCISIV132/122 does not support following coverage code with error report:
"ncvlog: *E, ECBECL… Range specification for a bin must start with (‘{’)"
/// ------------- coding start -----------------
bit [6:0] sbyte;
covergroup cg;
coverpoint sbyte {
bins mod3[ = sbyte with {item % 3 == 0};
}
endgroup
/// ------------- coding end -----------------
Can anyone give me feedback ?
Hi
I have installed Cadence IC615 in FEDORA 15. While invoking it by typing virtuoso, its giving folllowing error
"ERROR: Can not find any 32 bits or 64 bits executable version of "virtuoso""
Can you please suggest necessary modification to rectify the error.
Regards,
Darshak
Where can I get the equivalent circuit of device model? it is used in PSpiceAA. the model is one of aa_igbt library. It is more complicated than other IGBT model and it concludes more property name. I want to know what the property name acturely mean in CIRCUIT. In model text I can see "model 1613". Can I find the CIRCUIT of "model 1613"?
Thank U very much.
Hi all,
Can anybody guide me how can we do hierarchical access for covergroups.
The following is the scenario.
Module A has 4 covergroups
Module B has 4 covergroups
I want to use A and B covergroups for cross at top level.
Can anybody suggest me how i can do that.
Hi All,
I am using a vr ahb (eVC) and i get this error "Overflow, divider cannot be zero" . I have no clue how to debug this error. Coud anyone please throw some light on thsi error?
I have a vhdl code that has the following lines:
library ieee;
use ieee.std_logic_1164.all
library encode_8b10b;
library decode_8b10b;
The Cadence simulator is complaining about the encode_8b10b and decode_8b10b libraries:
"logical library name must be mapped to design library.
I tried putting the following into the cds.lib file:
define encode_8b10b ./INCA_libs/worklib
define decode_8b10b ./INCA_libs/worklib
That did not seem to work.
Anyone know how to map these libraries?
Thanks
Hi ,
Can anybody explain me how "option.weight" used..
if option.weight = 50 what happens and how it is going to effect the total coverage.
if option.weight = 0 what happen and how it is going to effect the total coverage.
Hi,
The following code gives an error with ncverilog. Can any one figure out why ? (version 12.2)
case(ratio)inside[990:1010]: mon_txn.bit_rate_captured =3'b000;[390:410]: mon_txn.bit_rate_captured =3'b001;[190:210]: mon_txn.bit_rate_captured =3'b010;[90:110]: mon_txn.bit_rate_captured =3'b011;[35:45]: mon_txn.bit_rate_captured =3'b100;[16:24]: mon_txn.bit_rate_captured =3'b101;[8:12]: mon_txn.bit_rate_captured =3'b110;endcase
(1)case (ratio) inside
ncvlog: *E,ILLPRI: illegal expression primary [4.2(IEEE)]
(2) [990 : 1010] : mon_txn.bit_rate_captured = 3'b000;
|
ncvlog: *E,NOTSTT : expecting a statement [9(IEEE)]
(3) [390 :410] : mon_txn.bit_rate_captured = 3'b001;
|
ncvlog: *E,ILLPRI : illegal expression primary [4.2(IEEE)].
(4) [390 :410] : mon_txn.bit_rate_captured = 3'b001;
|
ncvlog: *E,NOTSTT : expecting a statement [9(IEEE)].
and so on
When simulating a netlist containing integrated clock gate cells (icg), we have many of these cells that propagate unknown states ('x') due to the fact that the clock signal is initialized high and the latch in the clock gate cell is uninitialized. This causes problems during sim startup.
I was wondering if there is a common technique for dealing with this situation. Do you perform a 'force' to initialize all of the icg latches? Or is there some other technique that you prefer.
Thanks in advance for any advice!
All,
is there any way to customize the syntax highlighting in SimVision's console.
When I run UVM, messages and errors are automatically highlighed in different colors.
I would like to syntax highlight my own customized messages.
thanks.