Passing parameters form verilog to systemC

May 20, 2014, 2:23 am

≫ Next: Whether DPI - C functions can be used in the environment where the top is in C.

Hello,

I want to call a systemC function in a Verilog shell using a wrapper, and I want to pass parameters from verilog to systemC, using "ncsc_get_param" in systemc side.

But I have a problem, because it is necessary to put parameters in the verilog wrapper, whereas I want to put them in a higher hierarchy ...

Please tell me if that i want is possible or not ?

Sincerely , jean-Pierre

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Whether DPI - C functions can be used in the environment where the top is in C.

May 22, 2014, 9:32 pm

≫ Next: net connectivity at the top level using TCL

≪ Previous: Passing parameters form verilog to systemC

I have created a simple example for dpi functions. Below is the code:

CODE: C_file.c

#include "stdio.h" 
#include "svdpi.h" 
//int main()
//{
extern void export_func(void); 
void import_func() 
{ 
export_func(); 
} 
//}

CODE: SV_file.sv

module sv_file;export"DPI-C"function export_func;import"DPI-C"contextfunctionvoid import_func();functionvoid export_func();
$display("SV: Hello from SV ");endfunctioninitialbegin
import_func();endendmodule

I am running the code with the command,
irun –sv sv_file.sv c_file.c

The dpi functions are working fine as expected.

But this code is without main() function. When I try running the code with main function, the sv code is not able to find the import_func definition in C.
1. So I wanted to know whether dpi functions can be used in an environment where we have only C testcases instead without sv testcases (ie) C is in the top of the environment and execution starts and ends in C.
2. And, I am not able to run the code when I am trying to use only the export function (ie) calling the C-defined function in SV. Is it possible to use only the export function without import?

Your help will be very useful for me. Thank you.

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net connectivity at the top level using TCL

May 28, 2014, 1:41 am

≫ Next: Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

≪ Previous: Whether DPI - C functions can be used in the environment where the top is in C.

Hello,

I would like to use ncsim's (or simvision's) shell to find out the connectivity of a net.

For example, if I have a wire named clk in my top-level, I would like to get a list of ports that this wire is connected to.

Is this possible? Can you point me how to do that?

Thanks,

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Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

May 28, 2014, 2:40 am

≫ Next: Envelop Following Analyses for Switching Amplifiers

≪ Previous: net connectivity at the top level using TCL

Hi,

I am now working on a AMS verification using irun. I have an analog module (Verilog-AMS model, .vams) and a logic module (SystemVerilog RTL netlist, .sv) and want to integrate them together for system verification, especially on the control of the analog module by the logic one. The testbench I am using is in .vams format. When I compiled it with irun, it gave the following error message and I don't know how to fix it. May I know if you have an idea on this issue? Thanks a lot in advance.

ncvlog: *E,WOUPSR (/rtl/sv/dtcm_dsc_enc_ich.sv,293|27): A reference to an entire array is not permitted in this context [SystemVerilog].
(`include file: /rtl/sv/dtcm_dsc_enc_ich.sv line 372, file: all.sv line 121)
history[i] = history_m[i];

Best Regards,

Solomon

↧

Envelop Following Analyses for Switching Amplifiers

May 28, 2014, 11:09 pm

≫ Next: K*itc*he*n Reviews UK

≪ Previous: Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

Hi..,I want to do envelop following analyses in cadence for switching amplifiers, as tutorial contains the example in which linear amplifier is used and the same is not working perfectly with switching amplifier so,I'd like to ask the question that Is there any separate procedure for the envelop analyses of switching amplifier?

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Kitche*n Reviews UK

May 31, 2014, 5:03 am

≫ Next: I can't find "Part Manager" option in OrCad 16.3

≪ Previous: Envelop Following Analyses for Switching Amplifiers

K*itc*he*n Reviews UK. Thirty Ex Display K*itc*he*ns To Clear. w*w*w exdisplayk*itc*he*ns1 c*o u*k £ 595 Each with app*liances.

w*w*w stilh*ausk*itc*he*nsreview c*o u*k

↧

I can't find "Part Manager" option in OrCad 16.3

December 7, 2012, 10:10 am

≫ Next: Viewing Verilog Tasks in Simvision

≪ Previous: K*itc*he*n Reviews UK

Hy!

Have you any idea, where is this "part manager" option from my OrCad 16.3?

http://www.youtube.com/watch?v=AZRVEKfXfIc

Here is my screenshot:

http://www.hobbielektronika.hu/forum/getfile.php?id=184650

Thanks!
Balint

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Viewing Verilog Tasks in Simvision

June 2, 2014, 9:39 am

≫ Next: Black boxing issue in IFV

≪ Previous: I can't find "Part Manager" option in OrCad 16.3

Hi,

I have the following probe.tcl file included in my simulation:

database -open waves -into waves.shm -default
probe -create -database waves -all -depth all -tasks
run
exit

In the past I have been able to see the tasks in Simvision as small tick marks, but I can't seem to get them to show up. How can I see when my tasks are executed?

I'm using INCISIV131.

Thanks,

Chris

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Black boxing issue in IFV

June 3, 2014, 4:12 am

≫ Next: ADE L Outputs Window does not work

≪ Previous: Viewing Verilog Tasks in Simvision

I am facing problem while black boxing to end-IPs. The one IP contains signal which helps to start the system. So, I can't do black box to it. Still I want to check connectivity between those two IPs. What should I do?

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ADE L Outputs Window does not work

June 12, 2014, 2:23 pm

≫ Next: Bind SVA to VHDL Enumerated Type

≪ Previous: Black boxing issue in IFV

The way I have always probed currents/voltages in ADE was to go to "Outputs>to be plotted>select on schematic" and click every node/pin I need. Now that I've moved to a new system this function does not work. The nodes show up in the outputs window, but when I run a simple single point dc analysis they do not appear.

details:

- I can annotate the node voltages and device operating points on the schematic with no problems

- If I use the calculator to form an equation (i.e. 'VDC("/OUTPUT")', and copy paste it in a row in the output window it will show up as expected, but it takes forever to do this for several nodes/currents.

- This is while using spectre

There seems to be some disconnect between the saved data and the display on the ouputs window. Anyone have a clue?

Thanks.

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Bind SVA to VHDL Enumerated Type

June 13, 2014, 8:04 am

≫ Next: In UVM is there any Inheritance like "Specman e when Inheritance"..

≪ Previous: ADE L Outputs Window does not work

Hi,

I’m writing SystemVerilog assertions to check a VHDL state machine, and I need to bind the assertions to the VHDL component. What is unclear is how should I write the module port list? For example, the assertion should looks something like this:

property p_state_chk;

@(posedge clk)

state == ST2 |-> $past(state,1) == ST1;

endproperty

The signal state is defined as an enumerated state in the VHDL source, similar to the following:

type state_type is (ST1, ST2, ST3);

-- signal declarations

signal state : state_type;
I've declared a port in the assertion module similar to the following: package enum_pkg;
typedef enum {ST1,ST2,ST3} smpl_st_t;
endpackage module comp_chk (clk,state); input clk;
input enum_pkg::smpl_st_t state;endmodule The binding is accomplished like this: bind comp comp_chk u_comp_chk (.clk(clk),.state(state));

However, I continue to get elaboration errors (E,CFMPTC). How can I bind the above assertion to the VHDL enumerated type? Is the enumerated type in the assertion module defined as a string, and bound to the VHDL component? Is using $nc_mirror an option?

Thanks,

Tony

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In UVM is there any Inheritance like "Specman e when Inheritance"..

June 14, 2014, 7:03 am

≫ Next: Functional Coverage Question

≪ Previous: Bind SVA to VHDL Enumerated Type

Hi all,

I need following Information,

In Specman e:

we are able to Create field inside the struct like

sample Code:

when WRITE'trans_type

{

addr: uint[31:0];

};

when READ'trans_type

{

addr: uint[8:0];

};

In UVM:

If I want to create a field in parent Class using Inheritance is Possible... I have Better Knowledge in Spceman e. I am new to UVM due to comparing those Environment feature I got this Doubt...

Please any body Share your Knowledge to Update myself...

Thanks,

Selvavinayakam.na

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Functional Coverage Question

June 22, 2014, 8:19 am

≫ Next: UVC Source Synchronous Interface

≪ Previous: In UVM is there any Inheritance like "Specman e when Inheritance"..

I have 2 coverpoints.

Each coverpoint has auto generated bins as well as user-defined bins. In pseudo-code, I will describe them as follows:

cp1:

auto_bins,

userdefined_bin0, userdefined_bin1 ;

cp2:

auto_bins,

userdefined_bin2, userdefined_bin3 ;

Now, I want to cross cp1 and cp2. But, in that cross-coverage, I am only interested in crossing the userdefined bins and not the auto_bins.

cp1_x_cp2:

cross cp1, cp2 {

userdefined_bin0 intersects with userdefined_bins_2, 3 ;

userdefined_bin1 intersects with userdefined_bins_2, 3 ;

**************** This is being achieved but the auto bins are also coming into play.

*************** How do I ignore the auto bins??

}

Thanks,

ashfaqh

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UVC Source Synchronous Interface

June 25, 2014, 2:15 pm

≫ Next: Breakpoints in simvision(Incisiv Simulator)

≪ Previous: Functional Coverage Question

I am attempting to develop a UVC with a source synchronous interface. I need to be able to control the flow of clock and data to the DUT such that when requested, the clock and data are gated off (essentially, the interface is disabled).

Controlling the flow of data is relatively straight-forward. Where I'm getting wrapped around the axel is with the clock. How can I drive the clock from the driver such that is can gated off/on?

↧

Breakpoints in simvision(Incisiv Simulator)

June 27, 2014, 2:48 am

≫ Next: How can I dump waveform using irun uder UVM environment

≪ Previous: UVC Source Synchronous Interface

Hi,

I started using simvision(Incisiv Simulator) in my project recently. I have set few breakpoints in few files. Is there a way to save the breakpoints that I have marked in this run, so that I can load the same breakpoints in some later run? (This will be very handy in debugging process)

Any inputs will be of great help.

Thanks,

Subrahmanya

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How can I dump waveform using irun uder UVM environment

June 28, 2014, 3:17 am

≫ Next: Setting vhdl tb generic using irun command

≪ Previous: Breakpoints in simvision(Incisiv Simulator)

I downloaded an example (uvm_phases.tar ) from this website

http://www.testbench.in/UT_02_UVM_TESTBENCH.html

I try to download the waveform with a tcl file

database -open waves -shm

probe -create -database top -all -depth all

uvm_phase -stop_at -end connect

run

exit

but I get no signal from the waveform

the top module is as follows

`include "uvm_macros.svh"

import uvm_pkg::*;

`include "driver.sv"

`include "monitor.sv"

`include "agent.sv"

`include "env.sv"

`include "test.sv"

module top;

initial

run_test();

endmodule

and my makefile is as follows

ius: ${FILES} ${IFILES}

@if [ ! -e ${UVM_HOME}/src/uvm_pkg.sv ];then \

echo "*******************************************************";\

echo "Environemnt varible UVM_HOME is not set or points to incorrect path"; \

echo "*******************************************************";\

irun ${UVM_FLAGS} +incdir+. ${FILES} +UVM_TESTNAME=test1 -access +rwc -input input.tcl

↧

Setting vhdl tb generic using irun command

July 1, 2014, 4:54 am

≫ Next: increase virtual memory to sn_compile.sh

≪ Previous: How can I dump waveform using irun uder UVM environment

Hi all,

I've got a problem. In my tb I've got a generic:
G_WAVEFORM_TYPE : string := "xxx"

and i'd like to change "xxx" to "yyy" using irun "start.f" file, but i can't

-mess -v93 -assert ../src/dut.vhd ../src/tb.vhd -generic "tb.G_WAVEFORM_TYPE => "yyy""
or in other file:
-top tb -access rwc -defparam tb.G_WAVEFORM_TYPE="yyy" -nowarn CUDEFB
doesn't work. Could you tell me how to set a tb (vhdl) generic from *.f file using irun -f and what is the correct command to do it?

Thanks,
John.

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increase virtual memory to sn_compile.sh

July 10, 2014, 8:02 am

≫ Next: How I can get test status from specman e at sv testbench

≪ Previous: Setting vhdl tb generic using irun command

How do I increase the virtual memory allocated to sn_compile.sh? We have an environment compilation crashing because of an “out of virtual memory” error.

↧

How I can get test status from specman e at sv testbench

July 17, 2014, 2:08 am

≫ Next: Capture project conversion

≪ Previous: increase virtual memory to sn_compile.sh

Hi, all!

My UVM-SV testbench inncludes e vip. At the end of test specman prints status:

Checking the test ...
Checking is complete - 0 DUT errors, 0 DUT warnings.

Can I get the number of DUT errors at SV level?

↧

Capture project conversion

July 17, 2014, 3:22 am

≫ Next: ICCR: toggle exclude for bits of a bus

≪ Previous: How I can get test status from specman e at sv testbench

Hi all,

I have a project (.OPJ & .DSN) made with Orcad 16.6, and I have an older release of Orcad (10.3). When I attempt to open the project within Orcad 10.3, The DSN file can't be loaded.Capture shows me this error message : "Attempt to read a design file which is not supported by this version of database".

How can I "convert" my filesinto an older version of the DSN format, to be readable with Capture CIS 10.3 ?

Best regards,

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