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Binding systemverilog modules (module ports' directions)

August 19, 2014, 5:49 am
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Hello,

I'm using some binding modules in sytemverilog VIP. They are binded to VHDL modules.

The systemverilog modules' ports are all defined as logic without  specifying direction (input, output or inout).

Compilation passes without any errors. Elaboration fails. It requires direction to be specified for some ports in sys-verilog bind modules definitions as te direction for the VHDL modules.

This isn't the case with modelsim which doesn'r produce elaboration errors.

Also Why this is required for some ports and not all the ports ?

The error code is: ncvhdl_p: *E,CFMPMC

And an example on the eror msg is: "(./INCA_libs/irun.lnx8664.11.10.nc/.cdssvbind/cds_tmp_svbind0000422d_a8c0620a_0x2a003d41.sva,2|762): Port mode mismatch: Verilog(fsm_sink_bind.send_ack) is mode 'input'; VHDL(FSM.SEND_ACK) is mode 'out'."

Note that it says  fsm_sink_bind.send_ack direction is "input", although I declare it as logic without specifying direction !

 

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coverage on e Temporal checks

August 12, 2014, 10:28 pm
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Hi

    I am trying to get functional coverage on the temporal checks in my e based verification environment. I added the  specman_pre_command "configure cover -collect_checks_expects=TRUE" in my simulation script. I also have the specman_pre_command "configure cover -specview_cover_window" to view the old specman coverage window. My queries are

 1. I read somewhere that temporal expression coverage can be collected  only with IMC tool.Is it true. In my current setup with collect_checks_expects variable i am not able to see th TC coverage where as i am able to see other coverage blocks.

 2. I tried to get coverage DB in IMC format with "-coverage block:functional" in the ncelab phase. After running the simulation icc_<des_csum>_<ver_csum>.ucm file is generated for code coverage but sn_<des_csum>_<ver_csum>.ucm is not generated for functional coverage. And the functioanl coverage ucd file is generated as sn.ucd instead of sn_<>_<>.ucd. For code coverage the ucd file is generated in the icc_<>_<>.ucd format.

   Any help in resolving this issue if greatly appreciated.  

 

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Setting time resolution using irun

August 21, 2014, 8:32 am
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Can I change time resolution using iruns scripts?

Command: irun -input setup.tcl 

Script: 

database -open waves -into xxx.shm -default -event

probe -create -all -depth all

run 2ms 

Now I have got on my simvision waveform time resolution equals 1 ps.

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Z state check inside SV

August 22, 2014, 5:52 pm
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I am using cadence irun to run the mixed signal verification. I am trying to see if real value i am getting is has open drained or not. How do I check Z state of real value in testbench. 
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How to implement soft reset or functional level reset in vr_ad register model?

August 25, 2014, 4:25 am
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Hi all,

In my project in the register model i have some fields which are sticky i.e. they are not effected by reset.For such fields how to implement in vr_ad? If it is possible, is there any chance to implement dircetly from the IPxact script(With the help of verdor defined extensions)?

 Please help me in this regard.

Thanks in advance,

Subhash. 

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ncsim: *F,INTERR: INTERNAL EXCEPTION

August 25, 2014, 11:01 pm
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Hi, Sir,

 

I meet the following error :

 $xana_source in ...........

ncsim: *F,INTERR: INTERNAL EXCEPTION

Observed simulation time : 0 FS + 0

TOOL: ncsim(64) 11.10-p001

HOSTNAME: shacs201

OPERATING SYSTEM: Linux 2.6.18-194.e15 #1 SMP Fri Apr 2 14:58:14 EDT 2010 x86_64

MESSAGE: sv_seghandler - trapno -1 addr(0x0031F698)

 

Can you help ?

 

Thanks 

 

 

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Filtering UVM info messages

August 26, 2014, 3:26 am
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Hi,

I would like to ask if there is a way of filtering uvm_info messages output during simulations.

I am interested in messages coming from one particular uvm_component.

Does SimVIsion have a feature like that?

 

Thanks,

vito

 

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Simulating basic Log Amplifier and Antilog Amplifier using diode as well as transistor

August 26, 2014, 12:40 am
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I'm learning the basics of Cadence OrCAD 16.6 Lite. I want to design and simulate the basic Log Amplifier and Antilog Amplifier circuits both using diode as well as transistor. I'm able to design these circuits. What values should be provided to the diode and transistor? In order to verify the simulation output, I have to calculate the output voltage theoretically, which needs the values of saturation currents for the diode and transistor. How to find these values? I have used the component DIODE from DISCRETE library and NPN BCE from TRANSISTOR library. Also tell me if I have chosen the correct components or not.
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Error while invoking Cadence IC615 virtuoso

August 1, 2014, 3:27 am
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 Hi

I have installed Cadence IC615 in FEDORA 15. While invoking it by typing virtuoso, its giving folllowing error

"ERROR: Can not find any 32 bits or 64 bits executable version of "virtuoso""

 Can you please suggest necessary modification to rectify the error.

Regards,

Darshak

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ncsim: *E,IMPDLL: Unable to load the implicit shared object

September 3, 2014, 12:27 am
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Hi,
While running simulation , i am getting the below mentioned error .
Can anyone help me to fix this error.

ncsim: *E,IMPDLL: Unable to load the implicit shared object.
OSDLERROR: /prj/.../v/_sv_export.so: failed to map segment from shared object: Operation not permitted.
ncsim: *W,LIBRUN: Could not load the dynamic library: ./INCA_libs/irun.lnx86.13.10.nc/librun
System ERROR: ./INCA_libs/irun.lnx86.13.10.nc/librun.so: failed to map segment from shared object: Operation not permitted.
ncsim: *F,NOFDPI: Function main not found in any of the shared object specified with -SV_LIB switchncsim: *E,IMPDLL: Unable to load the implicit shared object.

Thanks
Sidharth

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ncsim: *E,IMPDLL: Unable to load the implicit shared object.

March 19, 2012, 2:36 am
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Hi All,

 anyone encounter below issues when running OVM ? how to resolve this issue ?

ncsim: *E,IMPDLL: Unable to load the implicit shared object.

Thanks

Simon

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changing the name of waves.trn file

September 3, 2014, 5:53 am
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Hi,

Does any one know how to change the name of waves.trn located in waves.shm directory during simulation ?

Is there a command-line option that can be passed to irun to do this ?

This is because every time I run a simulation using irun, the old waves.shm/waves.trn file is overwritten by the new one.

 Thank you

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One hot assertion in RTL

September 4, 2014, 8:51 am
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Hi,

What is the best way to add one hot assertion on a bus in verilog?

Ex: Wire [9:0] one_hot_wire; Only one of the bit of this wire is supposed to go high in the simulation otherwise it should fail. 

 

Regards,

Abhishek  

 

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ncelab: *W,MXWARN: Reached maximum warning limit for 'CUVWSP'(1000)

September 8, 2014, 11:04 pm
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Hi,

During gate level simulation i am getting below mentioned warning.

ncelab: *W,MXWARN: Reached maximum warning limit for 'CUVWSP'(1000)

After this  ncelab: *F, INTERR EXCEPTION is coming.

 

How to ignor the warning and continue the simulation ?

Thanks,

Sidharth 

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Gate level simulation flow with cadence

September 8, 2014, 11:39 pm
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Hi,

I am new to gate level simulation.

Can anyone guide me for steps involving gate level simulation using incisive simulator.

I am using irun insted of ncsim and i have a netlist and a sdf file.

Please guide me.

Thanks,

Sidharth 

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Gate level simulation with netlist and other RTL files

September 10, 2014, 11:19 pm
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Hi,

In my top level environment there are several modules are instantiated and one of the module is replaced by netlist.

i am facing  *F,INTERR: INTERNAL EXCEPTION.

Netlist should be top file or it can be instantiated inside other module. 

Pls help me.

Thanks

Sidharth 

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Exclude signal in IMC in command line

September 16, 2014, 1:09 am
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Hi,

I met some issue to exclude signal in IMC.

In fact, I'm using the syntaxe given in the help example of IMC HELP as follow:

exclude -inst lib.inst_a(rtl):inst_b:inst_c (WORKING THE INSTANCE IS EXCLUDE)

exclude -inst lib.inst_a(rtl):inst_b:inst_c -toggle rst (NOT WORKING: *W,NOMATCH: No matching entities found for argument 'lib.inst_a(rtl):inst_b:inst_c/rst)

 I have try several write of the command line whitout succes.

 Thank for your help,

BR,

Julien

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Accessing vplan attributes from console

September 22, 2014, 3:24 am
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Hi All,
Does anyone know anything about the API to access vplan attributes from the console or from an e program ? 
Specifically I want to be able to output this data in an arbitrary text format.
 
I know that I can already export a csv file using some batch API commands as shown below but I would like to directly access the parameters such as NAME and SIMULATION_ABSOLUTE_GRADE and then output them myself.
 
Has anyone done this or does anyone know how to do it ?  
 
 
<'
extend global {
  dump_vplan ( result_file_name:string=NULL) is {
    vm_manager.set_global_config("time_format","%F %T");
    if result_file_name == NULL { result_file_name = "results.csv"; };
    var all_sessions := vm_manager.get_all_sessions();
    var params: vm_export_vplan_parameters = new;
    params.set_vplan_tree_depth(1);
    params.set_information_kind(SECTIONS);
    var attrs: list of vm_vplan_attribute_t;
    attrs.add(NAME);
    attrs.add(SIMULATION_ABSOLUTE_GRADE);
    params.set_attributes(attrs);
    params.set_target_file(result_file_name);
    params.set_override_target_file(TRUE);
    vm_manager.export_vplan(params, all_sessions);
  };
};
'>
 
thanks in advance,
Andy 
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Assertion detect *WORNG* fell of line due to gated clock

September 28, 2014, 1:11 am
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Assertion detect *WORNG* fell of line due to gated clock

 Simulation assume line was high and on the posedge of clock the line is constant low and detect it as FELL and assertion is active due to that and cycle after fail!

 assert property ( @(posedge TxByteClkHS) disable iff(!rst_sys_n) 

      $fell(TxRequestHS) |=> $fell(TxReadyHS) );  

Tought to add ##1 cycle delay before every assertion, but the solution is not very good. 

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Gate Level Sim - SDF annotation debug

May 23, 2013, 4:22 am
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Hi, 

I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour.

When I annotate using just the netlist, cell_lib and sdf , everything works fine. However, when I try to annotate using the testbench and providing the full scope to the netlist within the verification environment (SCOPE=test_env.<scopetodigtop>.udig_top), I see thousands of 

SDFNEP, SDFNET errors. The paths and timing checks which ncelab is complaining about definitely do exist in the cell_lib verilog, and the scope is definitely correct. I have tried modifying the scope just to make sure that it was correct and with anything apart from these settings the annotator complains that the scope is incorrect and refuses to proceed.

What am I missing and what is the best way to debug this ?

I have tried versions incisiv/11.10.011, incisiv/12.10.011 and incisiv/12.20.008 

thanks

Andy 

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