Hi all,
I am trying to to set some vr_ad_reg fields with the set_value() method.
This method require that the value will be passed as rf_value_holder struct , however I didn't find any good description or example on how to do so.
I am asking for help on understanding how to do it, the CDNSHELP document on this subject is insufficient.
Regards,
EM.
Hi,
I have a testbench in which each test case adifferent assertion module. The assetion module is a top level in heirarchy(parellel to my test bench top which instantiates DUT). I need to dump the waveform for these assertion modules using shm_dump.Is there any way to do it without editing the shm_probe after each test case run.
I tried $shm_probe( $root,AC); , $shm_probe(*,AC).... but that gives compilation/elab errors
Thanx in advance
I need to do a full read/write/softreset test on register module and need to enumerate the fields of all the registers, but I checked the help documents and didn't find the solution. Could anyone tell me how to enumerate that?
I'm sure this is a frequently asked question (FAQ)
When we turn on SVA in our simulations, some of our long-running concurrent assertions are triggering failures at the end of the simulation. It appears the assertion triggered, but the simulaiton $finish before the assertion had a chance to complete (either vacuously-succeed, or normal succeed.)
When the assetoin-report is issued, these 'dangling' assertions are classified as failures.
Is there a way to change the report, or change the assertion-behavior so dangling-assertions are not reported as failures?
Hello all,
I want to call a C function within my systemverilog file using DPI C. I have tried the one step (irun -sv hello.c hello.sv )and it worked very well. But the thing I want to do is to create my own shared object .so, to do this I have tried a 3 steps methodology (ncvlog ,ncelab and ncsim) but it failed when I want to simulate it.
I got this message : ncsim: *F,NOLWSV: Searching for import subroutine "print" in default library libdpi. Unable to load the default library libdpi.OSDLERROR: ./libdpi.so: only ET_DYN and ET_EXEC can be loaded.
Please find in this following paragraph all my files and script to do this.
Thank you by advance,
Jean-Pierre
/////// top.sv
Hello all,
I have a traditional testbench that instantiates a Stimulus Generator and a DUT. Looks like this
//in module tb.v
module tb;
driver i_driver(...);
dut i_dut(..);
endmodule
The stimulus generation occurs within the driver.
I would like to add an UVM Environment with only a Monitor, Scoreboard and Functional Coverage to this testbench. I created a wrapper called "svid_packet_monitor" and instantiated that in the tb.
module tb;
driver i_driver(...);
dut i_dut(..);
svid_packet_mon_wrapper i_svid_packet_mon_wrapper();
endmodule
I am new to the whole UVM thing and am not sure how the code inside the monitor wrapper should look like. I took a first stab at creating a package with the monitor and associated class items and imported this inside the svid_packet_mon_wrapper. Then I created my_test inside the wrapper that extends uvm_test but I am not sure how to start this up. I am attaching the code for the monitor package and the monitor wrapper( with questions inside the monitor_wrapper code ). Any help to put this together would be highly appreciated...
Best
Raj
Hi all,
I got error since I use env.cmd file and setenv commands. Below, this is what the compiler show me:
../RTL/analog_mux2_ent.vhdl:
S : in real_vector (2**INPUTS_SEL-1 downto 0);
|
ncvhdl_p: *E,IDENTU (../RTL/analog_mux2_ent.vhdl,12|24): identifier (REAL_VECTOR) is not declared [10.3].
errors: 1, warnings: 0
With real type I've gor no error, but with real_vector I've got this error. Can you help please ?
I can use cbreak for example, to add a DEV=5% to its cap value.
but how can I add a tolerance to a switch(sw_tclose) part, there is not a tclose part in the breakout library.
I want the switch close at time 100ns+-10ns for example, how to do it?
I right click on the sw_tclose part, and chose "edit pspice model" , try to modify it , but not right?
how to do it ?thank you
Hi all,
I'm stuck on a simple issue but can't get out of it: I would like to generate severals waveform signals for my future testbench but the frequency of my signals are not correct.
Below is the code I want to simulate:
library ieee;
use ieee.std_logic_1164 .all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity triangle_generator is
generic(AMP: real;
OFFSET: real;
FREQ: real;
PHASE :real);
port(wave1: out real);
end triangle_generator;
architecture archi of triangle_generator is
signal tmp1 : real := 0.0;
begin
P1:process
constant delta : real := 1000.0e-12;
constant fin : time := 1000 ps;
variable angle : real := 0.0;
variable t : real := 0.0;
variable PHASE_RAD : real := 0.0;
begin
PHASE_RAD := (math_2_pi * PHASE)/360.0;
loop
angle := math_2_pi * FREQ * t;
t := t + delta;
tmp1 <= OFFSET+(AMP/2.0)*(2.0/math_pi)*arcsin(sin(angle));
wait for fin;
end loop;
wait;
end process P1;
wave1 <= tmp1;
end archi;
When I simule this code with FREQ=100 000 000 Hz I get the waveform in attachment, not really what I wanted. So I was thinking, if I write delta = 1000.0e-15 maybe it will be right, but absolutly not. When I change the value of delta, the frequency of the waveform is wrong.
So can you help me to get through this please?
Hi,
I am unable to to create a coverpoint using with it is giving an error . My code is as
cp_in1 : coverpoint in1 {
bins b1[ = in1 with ($countones(item) == 3);
}
Here in1 is a 8-bit variable. I am using INCISIV 13.10.013.
So please tell me how do i create the point for this.
Thanks
Srikanth M.
hello everyone,
I have a question about DPI-C , i know i can load a shared object using irun, even if you need to call it libdpi.so to load it . But I want to load several shared object and not only using the default "libdpi.so" ? because i have several shared object corresponding to a function, and i want to call several function from different shared object ...
Is it possible to do this ?
thank you by advance,
Sincerely,
Jean-Pierre
Hi Guru,
Is there a way to use IFV to show another/next counter example besides the one that is shown after using the debug "assertion" command?
That would be very helpful.
Hi,
I'd like to be able to dump the hierarchy of a design thats been loaded into simvision into a file, is this possible?
Ideally I'd like
Instance_name, Module_Name, Source_file
sub_instance_name, sub_module_name, source_file
sub_instance_name, sub_module_name, source_file
Instance_name, Module_Name, Source_file
...
Regards,
Hi There,
I want to run interactive mode since my simulation hangs and want to find out the loop. I have a tcl file which containts huge number of force statements and it takes extremely long time to let all force statement to finish. I believe, this happen due to continuous transfer of control between tcl and tb. I want to set a break point after all the force statement executes. So basically, till I finish all force statements from tcl, I want let irun run in regular mode and then after it want to switch to interactive mode to debug the loop.
Hi
I am new to UVM and I am getting following error.
Can anybody please help me out
my_sequencer#(my_trans) sequencer
ncvlog: *E,CLSMIP (./sv/my_agent.sv,25|34): Too many class instance parameter assignments.
Thanks in advance
Hi,
I'm running ams simulation for digital (verilog) and analog (schematic) blocks in a single testbench using hierachy config.
In topcell.vams, I instantiated i_cellA cellA(), and chose cellA as schematic in config file.
The irun.log error is "instance 'i_cellA' of design unit 'cellA' is unresolved in 'worklib.topCell:vams'.".
If I replace schematic view of cellA with an empty(port only) verilogams view, there will be no errors.
Thanks a lot.
icfb 5.10.41.500.6.149
mmsim 13.10.066
I'm getting a blank screen when I start emanager.
The console works fine, but the Incisive Enterprise Manager looks like this:
http://imgur.com/SR8G7Gg
Hi everyone,
I'm quite new to PSPICE and specific to Monte Carlo(MC) simulation. When follow the MC examples in UG, I can ony use simple output variable such as V or I of a node, but now I want the output variable be more complex such as impedance of a circuit so I key in V/I but PSPICE raises error. Anybody can tell me how to correct the output variable or work-around for this case will much help me!
This Forum is probably the best forum that i have ever used and i would just like to say how proud i am to be a member of this forum..