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AMS Supply sensitivity in a text based testbench

January 21, 2014, 4:15 am
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 Hi i'm having an issue where i'm running a VerilogAMS testbench, which can instantiate verilogams blocks or their schematic equivalents. The verilogams models have supply sensitivity statements on the IO pins, so that when running a purely verilogams flow, i have no issues. However when swapping one of the verilogams views for schematic, i get errors about supply sensitivity. 

I'm not sure how to set the supply sensitivity attributes for schematic views, when i have a text based top level/testbench. I can provide more information if required.

Can anyone help or point me to some documentatio?

I have also cross posted here:

http://www.designers-guide.org/Forum/YaBB.pl?num=1387738613

Any help would be greatly appreciated. Thanks.

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Poor generation distribution results using count() method.

January 22, 2014, 4:12 am
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Hi

I am facing some  problem using the count() method in list generation.

I have summarized it to the test case shown in the next code:

 <'
struct tc_s {
    name    : string;
    active  : bool;
    keep soft not active;
};

extend sys {
    l : list of  tc_s;
    keep l.size() == 10;
    keep for each in l {
        it.name == index.to_string();
    };

    keep l.count(it.active == TRUE) == 2;

    run() is also {
        for i from 0 to 20 {
            gen l;
            print l;
        };
    };
};
'>

When examining  the  generation results, I got all the items in the list to look like this:

item   type        name        active    
                                                                                                                                                
0.     tc_s        "0"         FALSE      
1.     tc_s        "1"         FALSE      
2.     tc_s        "2"         FALSE      
3.     tc_s        "3"         FALSE      
4.     tc_s        "4"         FALSE      
5.     tc_s        "5"         FALSE      
6.     tc_s        "6"         FALSE      
7.     tc_s        "7"         FALSE      
8.     tc_s        "8"         TRUE       
9.     tc_s        "9"         TRUE

The 2 last items always got the TRUE'active and the others not, why isn't it distributed over all the list items ?

Regards.

E.M. 

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Whats the difference between IES and IUS in cadence?

January 22, 2014, 11:31 pm
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Hi All,

I am new to Cadence simulator tools. Can someone please let me know the difference between the IUS(Incisive Unified Simulator) and IES(Incisive Enterprise Simulator)? Are there any difference in the features supported?

Thanks and Regards,

Prabhu Ilangovan

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Excluding Toggle coverage

January 29, 2014, 2:22 am
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Hi All, 

 

I am doing coverage part for my subsytem . I am using "set_toggle_excludefile" in my .ccf at the time of Elab . I am using patterns , so it is excluding some signals which are covered .i want to exclude only those which are not covered .

 I am using 12.2 version , ICCR. Please let me know any switch to exclude only uncovered toggles.

 Regards

Kiran 

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Cadence taking time for initialization

January 31, 2014, 10:46 am
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Dear Team,

I am running cadence in Ubuntu 12.04 32bit. While initialising/invoking any cadence GUI, it is taking relatively too much time(>10-20 sec). When it is running .cxt extention, it is taking time. Can you please tell me how can i solve this problem? Please find attached CDS log for your reference.

 Regards,

Darshak

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vr_ad register field printing

February 3, 2014, 2:47 am
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Hi,

I am doing vr_ad register reading and writing operations and able to print the register name and whole register data but unable to print the every filed name under that register and corresponding data. Please any one knows help me.

Thanks 

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timescale mismatch

February 3, 2014, 8:19 am
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Hi,

Does anybody know why the function in the code below is behaving differently when the input is a constant or a variable? It works for IUS8/20 but fails for incisive 12 or 13.
 
Rafael
 
-------
 
`timescale 1ns/100ps

module test;

  time time_var;

  initial begin
    $timeformat(-9, 0, " ns", 6);
    time_var = 1us;

    $display("first with variable");
    time_var = time_func(time_var);

    $display("then with constant");
    time_var = time_func(1us);

    $finish;
  end

  function time time_func (input time in_time);
    $display("we are in time_func, in_time = %0t",in_time);
    return in_time;
  endfunction

endmodule 
 


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Autochecklist

January 30, 2014, 12:26 pm
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 Hello experts,

Need your help in figuring out how to fillin the checklist form that I created. I can't seem to find my way how to do it.

Here's my scenario:

I created a form where it contain a checkbox next to a text. The text is a list of all the connectors on board layout (template). For example J01, J02, J03...J80.

What I needed to do is create a SKILL code that will look for these J connectors on a brd file. Once found the skill will place a checkmark on the checklist box.  When done looking for all of the J connectors, I then click a command button to go and delete the Via KO shape of each of the connector found.

 How do I go about this?

If you have a code in mind, may I please use it?

 

Thanks,

Eddie

 

 

 

 

 

 

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initial statement issue in IFV

February 7, 2014, 11:57 pm
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Dear Sir/Lady:

I have a question while using IFV, there is a simulation model in my design, after running the verification flow for several cycles, I did not find PRINET was set to  1b'1, this seems to be the issue related with initial statement, I do not know how to slove, could you help me? Thank you!

  =========================Command Line=========================

 iev +64bit *.sv +tcl+sim.tcl +covoverwrite +coverage+all

 =========================simulation model=========================

 module PRI(PRI);
  input PRI;
parameter RST_PULSE = 1;

reg PRINET;

initial
begin
 PRINET = 1'b0;
 #RST_PULSE
 PRINET = 1'b1;
end

endmodule

=========================TCL script file=========================

clock -add  ck  -initial 1  -width 1  -period 2 


force   sp  1'b1
force   cd  1'b0
force   d   1'b1

run 6

init -load -sst2 douglas.shm

init -show

constraint -add -pin sp 1'b1

constraint -add -pin cd 1'b0

constraint -add -pin d  1'b1

assert -add -block

assert -add -fsm

define constraint_trace on

define witness_check trace

prove

 

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probing all top mdules to a particular depth using $shm_probe

February 14, 2014, 10:06 am
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Hi,

 I have a testbench in which each test case adifferent assertion module. The assetion module is a top level in heirarchy(parellel to my test bench top which instantiates DUT). I need to dump the waveform for these assertion modules using shm_dump.Is there any way to do it without editing the shm_probe after each test case run.

I tried $shm_probe( $root,AC); , $shm_probe(*,AC).... but that gives compilation/elab errors

Thanx in advance

 

 

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merging three worklibs into one

February 19, 2014, 5:07 am
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we have a issue in merging 3 worklib( worklib_1,worklib_2,worklib_3 which has been created during compilation) during elaboration phase.

Command used for creating those worklib is:(top file - system.sv)

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv  -l verilog1.log -work worklib_1 -input ius.tcl -f verilog_1.f

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv -l verilog1.log -work worklib_2 -input ius.tcl -f verilog_2.f

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv -l verilog1.log -work worklib_3 -input ius.tcl -f verilog_3.f 

Command used for elaboration is:

ncelab worklib_1.system -cdslib ../simh/INCA_libs/irun.lnx8664.10.20.nc/cds.lib -hdlvar ../simh/INCA_libs/irun.lnx8664.10.20.nc/hdl.var -snapshot system:snapshot

we are getting the below error

ncelab: *E,NOUNIT: Unable to find a unit named 'worklib.system' in the libraries.

can anyone help us in solving the above error by providing the proper solution

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Code coverage exclusion case

February 19, 2014, 10:50 pm
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Code coverage has added an "all-false" bin for Verilog case statements that do not contain a "default" clause.

How to exclude a  default statement in  case statement in  code coverage while we simulate in cadence?
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Why $random is not controlled by seed?

February 24, 2014, 10:55 pm
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There is a segment of code below:

for(int i=0;i<10;i++)begin

$display("current random value: %0d", $random);

end

I use Cadence irun to compile and simulate this code. Although I add option " -seed random" to irun, but each time the result is same. It seems that $random is not controlled by -seed.

If I change $random to $urandom, it works! Each time I run, the result is not different.

So, my question is that, why $random is not controlled by -seed ???

Thanks.

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How to create coverage configuration file

May 8, 2012, 10:17 pm
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 I want to run    "set_toggle_excludefile"   command . And I pass this command to coverage configuration file . And run that file in elaboration command but it did'nt run.

 

where to create coverage configuaration file?

Elaboration command is directly run on terminal or give this command to run script or else???

 

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cadence ifv tool

March 3, 2014, 10:52 pm
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what is the methodology underlying in IFV tool during design verification.i.e I mean whether BDD based or SAT based.

If anyone knows please reply the answer or link of resource.

Thanks in advance. 

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Latest version of IFV

March 11, 2014, 12:15 am
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what is the latest version of IFV tool released from cadence? please reply soon.

 Thanks in Advance.

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CPF Simulations: Excluding PSL vunits

March 13, 2014, 1:11 am
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Hi,

I have a PSL vunit attached to my top level module (via PROPDIR), and this vunit contains some signals to implement some simple modelling.

The top level module is in a switchable power domain, and at the moment, when the power is removed, the PSL vunit is also "turned off". Are there any available options that exclude PSL vunints from CPF simulations?

FYI - the design language is VHDL and 13.20-p002

Thanks,

Steven

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Functional coverage of IFV tool

March 13, 2014, 4:51 am
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Can we check how much is the functional coverage of RTL design in Cadence -IFV tool  by using assertions  just like in test bench simulation and how to check the properties written for verification are covering the full design intent.

Thanks in Advance. 

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ncsim: *F,INTERR: INTERNAL ERROR

December 22, 2008, 1:17 am
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 Hi,

 Test : DRAM write and read up to 2GB . 

 Simulation fails with the following error. Can anbody please help me out?

ncsim(64): 06.20-p001: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncsim(64)       06.20-p001
  HOSTNAME: XIDCTEA1
  OPERATING SYSTEM: Linux 2.6.9-55.ELsmp #1 SMP Fri Apr 20 16:36:54 EDT 2007 x86_64
  MESSAGE: System virtual memory limit exceeded (0x100000d8/0x2b6bba4010)
-----------------------------------------------------------------

 

 

Note : I had checked the enough  physical memory and also virutaul memory available for the host.

Thanks,

Sankara

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NC: INTERNAL EXCEPTION

March 21, 2014, 1:08 am
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I got following informaiton, who can tell me why? Thansks.

By the way, I'm using a uvm enviroment.

 

ncelab: *F,INTERR: INTERNAL EXCEPTION
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncelab(64) 12.20-s012
  HOSTNAME: shalcs42
  OPERATING SYSTEM: Linux 2.6.18-274.el5 #1 SMP Fri Jul 8 17:36:59 EDT 2011 x86_64
  MESSAGE: xst_internal_error - default
-----------------------------------------------------------------
csi-ncelab - CSI: Cadence Support Investigation, sending details to /sdr/sdr_as/local_user/legsun/tb_pa587106_a1/sim/DMS/test/ncelab.err
csi-ncelab - CSI: investigation complete, send /sdr/sdr_as/local_user/legsun/tb_pa587106_a1/sim/DMS/test/ncelab.err to Cadence Support
irun: *E,ELBERR: Error during elaboration (status 255), exiting.
TOOL: irun(64) 12.20-s012: Exiting on Mar 21, 2014 at 15:35:20 HKT  (total: 00:00:16)

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