i want to check these assume properties are correct

November 21, 2013, 1:33 am

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Hi,

I wrote some of the assumptions in my fifo design and now  the assertion passing in my design.Before assemptions that assert property was failing.

 

assumptions are as below:

///Assumtion to check underflow: 

 assume_underflow :assume property(assume_property_underflow) $info("assumption holds"); else $error("Assumption failed underflow");

property assume_property_underflow;

  @(posedge clk)

  (!read && empty); /*$info("Assumption undeflow holds"); 

                                          else $error("Assertion underflow does not hold");*/

endproperty

///Assumtion to check overflow:

 assume_overflow :assume property(assume_property_overflow) else $error("Assumption failed overflow");

 

property assume_property_overflow;

  @(posedge clk)

  ((!write or !read) and full);  /*$info("Assumption overflow holds"); 

                                          else $error("Assumption overflow does not hold");*/

endproperty 

Please see these logics are correct? 

 

 

 

 

 

 

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Specman plusargs

November 26, 2013, 3:48 am

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Hi,

I would like to pass some parameters to my e testbench at run time. Does Specman have the nifty feature of plusargs (what SystemVerilog simulators have). A similar feature would also be welcome.

Thanks,

Tudor 

 

Stept through UVM code

November 29, 2013, 7:29 am

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Hi,

I'm trying to step through the SV UVM library code, but I just can't manage. I tried the built in library in IUS and also a version downloaded from Accelera. Both setups have -linedebug on the command line. When trying with the built in one, it says it was not instrumented for line debugging. The Accellera one lets me put breakpoints, the simulator stops there, but it doesn't show the execution point in the source browser (it just mentions in the console that it stopped at the specific line).

Is there something I'm missing?

Thanks and best regards,

Tudor 

Multi Language Intergration:integrating system verilog over e

December 4, 2013, 11:12 am

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Hi all,

  i have to integrate sv wrapper over e...

  if we integrate by using tlm_nonblocking_put we are facing below error please any body have an idea to resolve this error... 

 

*** Error: Unsupported template parameter of external interface port
The port 'uvm_test_top.sample_test.env.send_request_p' of interface
'tlm_nonblocking_put of any_sequence_item' has unsupported template parameter
'any_sequence_item'
Struct must contain at least one field which is configured to pass across
multi-language TLM transactions.

 

Thanks,

vinayak

 

e testflow

December 9, 2013, 5:15 am

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 Hi,

I am using e testflow, and encountering an interesting case that i would like to share and get your feedbacks.

I have an environment "A" with tf_domain == domain_a.

Under this  environment i am instantiating an environment "B" which is testflow unit and have 2 sequence drivers which are also testflow units.

According to the Cadence test flow document, if the tf_domain field is untouched, it is determined to be (with soft constraint) to be the same as the nearest enclosing testflow unit, if there isn't such  tf_domain is set to DEFAULT.

However, what i see is:

env_b.tf_domain = domain_a

env_b.seq_driver_1.tf_domain = domain_a

env_b .seq_driver_2.tf_domain =DEFAULT

How come the second sequence driver didn't got the same tf_domain value like the other units?

Moreover, the tf_domain field is declared as const, thus can not be changed after generation.

I will be happy to hear your feedbacks.

 

Is there any option like +ntb_random_seed in VCS for ncverilog?

January 31, 2013, 12:10 am

≫ Next: One question about system verilog `__LINE__ define

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I wonder how to generate random seed for simulation with ncverilog. Is there any option like +ntb_random_seed_automatic? Thanks!!

One question about system verilog `__LINE__ define

December 12, 2013, 5:59 pm

≫ Next: How to manually flush display message buffer to console?

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 There is a compiler derective in system verilog -- `__LINE__, it will expands to the current input line number. But I find it will return current line number -1.

For example, in below code(the left is line number):

1 initial begin
2 signal_a = 0;
3 signal_b = 1;
4 $display("current line is: %0d",`__LINE__);
5 end

When I run this code using ncsim, it will output:

current line is: 3

It's so strange, I think it should output "current line is: 4", because obviously this line number is 4, but not 3.

Can somebody tell me why?
Thanks a lot!

How to manually flush display message buffer to console?

December 12, 2013, 10:07 am

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Hi,

I have a few functions that take a long time to compute results. I'm trying to debug any performance problems. I know about the profiler and this has been of some use. No need to suggest this.

I'd like to print something on each iteration of the computation so I can get a real time sense for how the computation is progressing via live messages in the SimVision console window. However, Simvision seems to be buffering my $write(".")/$display() message until the end of the time slot.

   protected function void process_streams(adc_stream streams[);

    for (int i = 0; i < streams.size(); i++) begin

      for (int ii = 0; ii < streams[i].num_samples(); ii++)

        process_sample(streams[i].m_adc_samples[ii].sample);

      $write(".");

    end

    $display();

  endfunction

I see no dots printed to the console for minutes and then all of a sudden they all show up. 

 

Is there a SimVision option or command that'll cause messages to immediately be printed to the console window?

 

Thanks,

Ben 

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Using variables within range repetition expression in e

December 17, 2013, 4:14 am

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 Hi.

I am facing some problems with using var in  range repetition expression.

I have the next code :

a : unit;

b : uint;

keep b == a + 1234;

event e1;

event e2;

expect {@e1;[a]*@clk} => @e2 ; //  <== this works !

 expect {@e1;[a..b]*@clk} => @e2 ; //  <== this doesn't work !

I am geting the next error : 

 *** Error: first match variable repeat can only be used inside a sequence

Why ? does cadence supports such usage of the range repetition expresion ?

How do you recomend to workaround this problem ? (well beside the obivuos solution to replace it with TCM).

Regards,

E.M.

 

UVM register Coverage collection

December 19, 2013, 9:24 pm

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Hi

i have a question regarding UVM registers coverage collection. The UVM register file is generated by the tool and by default in new function of the uvm register the coverage is OFF like below

 function new(string name = "temp_register");
  super.new(name, 32,build_coverage(UVM_NO_COVERAGE));
 endfunction: new

In build phase of my tb environment i have  coded like below:

  uvm_reg::include_coverage("*", UVM_CVR_ALL);

 reg_model = ral_block_temp_reg_file::type_id::create("reg_model", this);
    reg_model.set_coverage(UVM_CVR_ALL);
    reg_model.build();

i am unable to see the coverage collection for UVM register,register fields and address map in verification plan tree of vplan in Vmanager. 

Can any one help me in this ?

Thanks in advance.

Vinod 

Communication between Verilog BFM and C-Based Verification bench

December 21, 2013, 11:41 am

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Hi

I have a SOC verification bench in C/ASM and integrated SV/Verilog based BFM/VIP. The system level tests are based on C/ASM.

To carry out functional simulations, the C/ASM tests are compiled, linked at the binary data of instructions are read into the On-Chip Memory for execution.

How can we enable the above environment where BFM(say its a master), waits for the system to reach to a point where system is ready and BFM(say its a master) can request data from/to the SOC?

To say in a short words, how can we achieve effective handshake between Verilog/SV(BFM) - C/ASM environments.

Could somebody please donate your ideas. 

 

Thanks
Arun

How to disable vr_axi checks

January 3, 2014, 3:49 am

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Hi I am new to vr_axi enviorment,in my testbench i have some axi interfaces. I want to understand how to disable vr_axi checks like below

"ERR_VR_AXI190***"

How to disable automatically-generated cross bins?

January 6, 2014, 1:19 am

≫ Next: What's the difference between Incisive_Enterprise_Simulator and Incisive_HDL_Simulator?

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 Consider the following example code:(it's an example in SystemVerilog P1800-2009, Page 500)

int i,j;
covergroup ct;
coverpoint i { bins i[ = { [0:1] }; }
coverpoint j { bins j[ = { [0:1] }; }
x1: cross i,j;
x2: cross i,j {
bins i_zero = binsof(i) intersect { 0 };
}
endgroup

Cross x2 has the following bins:
i_zero // user-specified bin for
(i[1],j[0]) // an automatically-generated bin that is retained
(i[1],j[1]) // an automatically-generated bin that is retained

My question is: if I only want the first bin, i.e. i_zero, what should I do? I don't want automatically-generated cross bins, I just want user-defined bins, is there some method to disable "automatically-generated cross bins"?

Thanks a lot!

What's the difference between Incisive_Enterprise_Simulator and Incisive_HDL_Simulator?

January 6, 2014, 6:56 pm

≫ Next: ICCR report generation issues for Multiple class instances

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 When I run RTL simulation by irun which is mainly composed of verilog and systemverilog code, sometimes it use Incisive_Enterprise_Simulator, sometimes it use Incisive_HDL_Simulator. So ,can someone tell me what's the difference of these two simulators? Why some simulation testbench should use IES, but some other testbench use  Incisive_HDL_Simulator?

I have just met a problem: when I run a test with irun command, it's queuing for one of the following license(s) -  Incisive_Enterprise_Simulator. But at this time there is a free license of Incisive_HDL_Simulator. Why not use Incisive_HDL_Simulator, but waiting for IES license? It seems some simulation can only be performed by IES? Am I right?

Thanks!

ICCR report generation issues for Multiple class instances

January 7, 2014, 8:11 pm

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Hi ,

 

I create class entry_information which is extends from uvm_componemt

in that entry_information class I have one cover_group entry_group which will be sampled for every posedge clk

 

I created  five instances of the class  entry_information from the monitor class

 

When I see the coverage report i am able to see only one instance of covergroup.  I’m using ICCR to generate the coverage report

 

class entry_information extends uvm_compoment

 

   bit x;

   bit[7:0] y;

   covergroup  entry_group();

      option.per_instance = 1;

      option.goal         = 100;

  

      entry_x : coverpoint x

       {

          bins x_cnt[4] = {[0:4]};      

       }

      entry_y : coverpoint y

      {

         bins y_cnt[6]  = {[0:6]};

      }             

    endgroup

 

 

     function new(string name = "entry",uvm_component parent);

      super.new(name,parent);

      entry_group = new(name);

      entry_group.set_inst_name(name);

    endfunction

 

endclass

 

 

class monitor extends uvm_monitor

 

  entry information entry_info[5];

 

  function void build_phase();

    

    string inst_name;

    for(int i = 0 ; i < 5 ; i++)

      begin

        $format(inst_name,"entry[%d]",i);

        entry_info[i] = entry_info::type_id::create( .name( inst_name ),.parent( this ));

      end

  endfunction

 

  task run

   forever

     begin

        @(posedge clk);

        for(int i = 0 ; i < 5 ; i++)

            entry_info[i].entry_group.sample();

     end

  endtask

 

Thanks,

Selvavinayakam.na 

---

What's the difference between -seed and -svseed in irun?

January 12, 2014, 7:00 pm

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There are two options to control random seed when using irun: -seed, -svseed.

It seems that these two options is doing the same thing: set a random seed to RNG. And I tried many times, I can't find difference between these two options. Both can be used to control Verilog/SystemVerilog randomization, for example:

-seed 123

-svseed 123

-seed random

-svseed random

So, what's the difference between these two options?

Thanks!

passing IRUN command-line arguments into vsif file?

September 8, 2010, 6:00 am

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Hi,

I use command-line arguments in my script and it looks like this

irun ... +define+MY_ARG ...

I can run stand-alone simulation with different MY_ARG to different tests.

How can I reuse my script in a vsif to launch regression of all tests? Is there a way to define an attribute so I can specify MY_ARG in vsif, for example

...

test my_test1 { my_arg_attr : 2};

test my_test2 {my_arg_attr : 3};

... 

Thanks for help.

Xing 

OS signal 11(segmentation violation)

January 12, 2014, 9:44 pm

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Hi,

I am getting OS signal 11 error and it is showing that I am using nested function in my code. What exactly the OS signal 11 error and why would we get this error. Please help me and thanks inadvance 

SystemC ncelab error

January 14, 2014, 6:26 am

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I'm trying to get a SystemC / Verilog simulation to run and am getting the following error messages:

There is no information on any of the warning or error codes in Cadence help or on this site. Has anyone got more information in these or suggestions on how to resolve them?

ncelab: *W,CUSRCH: Resolved design unit 'BLAH' at 'U_BLAH' to 'work.BLAH:v' through a global search of all libraries.
ncelab: *E,SCK109: complete binding failed: port is not bound to any interface: port 'tb.dut.signal_in' (sc_in)
In file: sc_port.cpp:247
In phase: end_of_elaboration.
ncelab: *E,SCK940: Error in SystemC elaboration
In file: sc_cosim.cpp:1249
In phase: end_of_elaboration.
ncelab: Memory Usage - 31.4M program + 72.5M data = 103.9M total (Peak 104.6M)
ncelab: CPU Usage - 0.1s system + 1.6s user = 1.6s total (2.2s, 74.7% cpu)
ncsc_run: *E,TBELABF: ncelab returned non-zero exit status
make: *** [comp_sc] Error 1

simvision : print window functionality

January 20, 2014, 10:51 pm

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Hi ,

I need to take a snapshot with a large number of signals.

I tried using file > print window. this prints the waveform as a .ps/.eps file. when this is converted to jpeg/png/bmp and opened

the snapshot is having very poor resolution.Please suggest any way to get good resolution image with the print window.

 Thanks in advance.