ncelab ncutilities E,BUILDF

May 17, 2013, 8:06 am

≫ Next: SimCompare - ignore time - compare only values

≪ Previous: files required to use vams netlist

Hi all,

Switching from release 10 to 12.2, I've found some problem with testbench which uses nc utilities.

ncelab (version 12.2) with option "-update" exit with :

---------------------------------------------------------------------------------------------------------------------------------------------------------------------

Updating: package NCUTILS.NCUTILITIES (AST)

/cadence/IS12.2/tools/inca/files/NCUTILS.src/ncutilities.vhd:

ncvhdl_p: *E,DLPAKW: Attempt to write package ncutils.ncutilities (AST)

into a read-only library.

errors: 1, warnings: 0

ncupdate: *E,BUILDF: Rebuild of unit package NCUTILS.NCUTILITIES (AST) failed.

entity worklib.tb_ncutil (AST) is already up to date.

ncelab: *F,DLUPFL: Update failed for entity WORKLIB.TB_NCUTIL (AST)

(unable to update).

---------------------------------------------------------------------------------------------------------------------------------------------------------------------

I didn't find clues on the web or in the docs,

Thanks,

Luca

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SimCompare - ignore time - compare only values

August 30, 2013, 6:42 pm

≫ Next: Cross coverage with ranges of a coverpoint

≪ Previous: ncelab ncutilities E,BUILDF

In SimCompare, is it possible to compare only the trace values and ignore the timestamps?

For example, given the two traces of the same signal but at RTL and SystemC

SystemC: 7@10ns , 10@20ns 10, 50@30ns

RTL: 7@50ns 7, 10@100ns 10, 50@150ns

if we ignore the timestamps, the traces are the same.

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Cross coverage with ranges of a coverpoint

September 4, 2013, 3:13 am

≫ Next: Help on using VPWL_F_RE_FOREVER

≪ Previous: SimCompare - ignore time - compare only values

I have a coverpoint with auto bins and I want to use this coverpoint ranges in a cross:

   logic [3:0] out1_unmute_thr;
   logic [0:0] 1l_ena;
   logic [0:0] 1r_ena;

c_1l_ena : coverpoint 1l_ena;
c_1r_ena : coverpoint 1r_ena;

c_out1_mute_thr : coverpoint out1_mute_thr iff(1l_ena || 1r_ena);

    out1_mute_thr_x   : cross c_out1_mute_thr, c_1l_ena, c_1r_ena {
      bins L = binsof(c_out1_mute_thr) intersect {[0:3]};
      bins M = binsof(c_out1_mute_thr) intersect {[4:11]};
      bins H = binsof(c_out1_mute_thr) intersect {[12:$]};
      ignore_bins of_ena = binsof(c_1l_ena) intersect {0} && binsof(c_1r_ena) intersect {0};
      }

I am trying to achieve a cross of the ranges of c_out1_mute_thr and c_1l_ena when only 1 and a cross of c_out1_mute_thr and c1r_ena when only 1. From this I would expect to see 6 coverage bins.

In IMC I only see three cover bins and I am also unable to view the bin values (The column is empty or N/A)

Please not that I do not want to create another cover point with the ranges or modify the original as i would lose the granularity (auto bins).

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Help on using VPWL_F_RE_FOREVER

November 1, 2008, 1:24 am

≫ Next: Missing module coverage

≪ Previous: Cross coverage with ranges of a coverpoint

Hi fellow designers! I get this error message while using the VPWL_F_RE_FOREVER. ERROR -- Invalid Time (.STIMULUS) in file "ordino_stims.stl" Line 13 I've spent hours browsing the PSpice Manual but there is no detail about VPWL_F_RE_FOREVER that could help me figure out the problem. Your advice will be highly appreciated. Thank you!

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Missing module coverage

September 9, 2013, 1:42 pm

≫ Next: Simvision list view

≪ Previous: Help on using VPWL_F_RE_FOREVER

Hello,

I am generating code coverage results for a design, but for some reason there are a couple of modules that are missing in the coverage report. I am using the imc tool to generate coverage, and have "-coverage all" specified when simulations run. I am not using the deselect_coverage, and there are no pragmas in the rtl to turn coverage off.

Has anyone else seen cases where certain modules for some reason do not get coverage results? Or what can cause this.

Thanks,

Kevin

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Simvision list view

September 16, 2013, 6:13 am

≫ Next: please help on verilog and vhdl combination problems

≪ Previous: Missing module coverage

Hi all,

In simvision is there a way to display signals in a 'list view'?, that is, each row represent a time value at which a signal changed and each column is a signal.

Thanks

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please help on verilog and vhdl combination problems

September 17, 2013, 8:31 pm

≫ Next: How can I transfer a integer variable from verilog to VHDL?

≪ Previous: Simvision list view

Hi Candence,

I met a problem in using verilog and vhdl:

1) I use verilog to make a testbench while the DUT all are made by VHDL

2) I want to initialize the lower level memories in DUT. I have tried to use $nc_mirror, but it seems useless.

So would you like to give me some suggestions on how to initial memories in VHDL designs through verilog testbench?

Thanks!

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How can I transfer a integer variable from verilog to VHDL?

September 18, 2013, 4:52 am

≫ Next: reinvoking from the tcl shell

≪ Previous: please help on verilog and vhdl combination problems

Hi Candence:

How can I transfer a integer variable from verilog to VHDL?

As the code shows bellow:

tb_top is verilog module;

vhdl_top and bellows are vhdl module.

module tb_top;

integer i;

$nc_force("tb_top.vhdl_top:ocmem:memarry[i]" , #data[i]);

endmodule

The ERROR message is:

expecting a integer index i.

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reinvoking from the tcl shell

September 22, 2013, 12:31 pm

≫ Next: Problem with GUI client on IES

≪ Previous: How can I transfer a integer variable from verilog to VHDL?

Hello,

I'd like to reinvoke the simulation using a tcl script. Is this possible? What's the tcl command to re-invoke the simulation?

Actually, I would like a script that runs a preamble command to update the simulation options contained in the irun.f file before re-starting the simulation. That would allow me to re-start the simulation with new options without leaving simvision.

Is this feasible?

thanks

↧

Problem with GUI client on IES

September 24, 2013, 3:14 am

≫ Next: CMOS INVERTER LAYOUT DEBUG!?

≪ Previous: reinvoking from the tcl shell

Hi all

I have recently started to suffer from this problem, when trying to open debugger window or modules window etc...

I am getting the next lines:

# Trying to communicate with GUI client (timeout in 60 seconds)
# Trying to communicate with GUI client (timeout in 40 seconds)
# Trying to communicate with GUI client (timeout in 20 seconds)
*** Error: Communication Timedout - Failed communicating with GUI client

does someone can point me to what might be the problem ? and how to solve it ?

it forces me to work only in batch mode, and it is really frustrating not tho have the ability to use the GUI.

Thanks,

me.

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CMOS INVERTER LAYOUT DEBUG!?

October 19, 2013, 12:44 am

≫ Next: interconnect check with PSL

≪ Previous: Problem with GUI client on IES

Hello all. So I am in the process of simulating my layout extraction. I ran DRC which was successful.I ran LVS which returned a negative output (my schematic netlist and extracted netlist DO NOT MATCH);however, I continued with the simulation hoping to see if I can gain some info from the plots...

Here is my layout and the plot of the simulation of the extraction (sorry for the bad quality layout image).

Please help me debug this issue. What should I be looking for?

Thank you. simulation LAYOUT

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interconnect check with PSL

October 23, 2013, 1:04 am

≫ Next: Different results for same netlist (in ADE-L & ADE-XL simulation)

≪ Previous: CMOS INVERTER LAYOUT DEBUG!?

Hi all,

I want to check interconnectivity among several IP blocks(in VHDL and Verilog) with PSL vunits. However I have a problem in binding. As I understand, i can bind the vunit to only one entity. But for interconnect check, I need port signals from both entities(IPs) so that I can continiously compare them. I can achieve this with SVA using SystemVerilog interfaces, but in PSL I am stuck.

Thanks for your help in advance,

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Different results for same netlist (in ADE-L & ADE-XL simulation)

October 25, 2013, 4:44 am

≫ Next: Multiply number, USING ISTIM

≪ Previous: interconnect check with PSL

Hello everybody,

I encounter the problem of differences in the results of ADE-L and ADE-XL simulations from the Virtuoso schematic editor, although I checked the netlists of both simulations to be equivalent (I used a text-file comparator to verify that). Both times spectre simulator is used.

Do you have an idea, what I could try out in order to find the reason for the differences in both simulations?

Thank you for your help!
Dominik

↧

Multiply number, USING ISTIM

October 25, 2013, 5:41 am

≫ Next: What is the desired phy response during LPI sendiing from GMAC to phy?

≪ Previous: Different results for same netlist (in ADE-L & ADE-XL simulation)

(a) Hey I have a function in a netlist where I want to multiply two numbers as follows:

.FUNC u() = a*b

But here I will not get the multiplication as asterisk will cause the rest of the line to be taken as a comment. What can I do?

(b) For the command

I top bot STIMULUS = (V(top)-V(bot))/Resistance()

I am getting the following error message

ERROR(ORPSIM-16346): STIMULUS <name> must be last
+ -V bot /Resistance .FUNC

What shall I do?

I am using Orcad Cadence version 16.5 and am a newbie to Pspice.

↧

What is the desired phy response during LPI sendiing from GMAC to phy?

October 27, 2013, 11:22 pm

≫ Next: Importing C Function into System Verilog using DPI with 3-step process

≪ Previous: Multiply number, USING ISTIM

Hello sir

I am sending LPI pattern from MAC to ethernet phy now I want to know that PHY is accepting my request and really goes into low power mode? because the pattern GMAC sends is correct but in Cadence VIP nothing is written for PHY response so how can I know phy is understanding my request of low power mode

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Importing C Function into System Verilog using DPI with 3-step process

October 31, 2013, 1:38 am

≫ Next: Formal Verification

≪ Previous: What is the desired phy response during LPI sendiing from GMAC to phy?

Hi all,

I want to import some C math function such as the sin and atan into my testbench using the DPI. It works fine when I use the "irum" command, the code should be right. But when I use the 3-step process it doesn't work. From the referrence manual I know that the c file should be first complied to the libdpi.so, but since I use the standare C function, which file should I compile? And I try to skip the compilation step and add the -sv_lib libm.so argument, it also doesn't work.

I greatly appreciate any help.

↧

Formal Verification

November 1, 2013, 1:29 am

≫ Next: Op-amp which can work at 100 kHz in PSpice

≪ Previous: Importing C Function into System Verilog using DPI with 3-step process

Please I'm beginner at Verification Field and shall anyone here recomment me to use formal verification and recommend me some materials.

what about simulation based Methodology ,, is it better for me ? I have been confused ,, thanks for helping me

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Op-amp which can work at 100 kHz in PSpice

October 30, 2013, 6:40 am

≫ Next: "No space left on device" Error!

≪ Previous: Formal Verification

I am looking for an op-amp which can be used as a comparator at 100 kHz frequency. I am using uA741 and it works fine upto 10 kHz frequency but not beyond that. Could anyone please suggest an opamp that works at 100 kHz in PSpice? Thanks!

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"No space left on device" Error!

November 6, 2013, 10:33 am

≫ Next: EMGR, how to disable auto complemetary scan filter

≪ Previous: Op-amp which can work at 100 kHz in PSpice

I'm trying to simulate a design for 50 minutes but Simvision hangs up at ~ 10 minutes with the following error:

error ncsim: *E, SST2ER: SST2 interface error: No space left on device.

The design successfully simulates for smaller times (i.e. 2 minutes). What is the cause? Should I try altering settings in my interactive tracefile? Like changing the probe command from "probe: create -shm -all -variables -depth all -waveform" to "probe: create -shm -variable -depth to_cells -waveform"?

Please advise. Thanks.