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IFV and IUS, what's the difference?

April 15, 2007, 7:26 pm
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Hello Cadence,

There are two similar simulation environment: IFV and IUS. Who know what's the difference with them? And one is another one's super set?

Best regards,
Davy


Originally posted in cdnusers.org bydavyzhu
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IFV run time errors

July 9, 2013, 1:37 pm
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Hi,

This is the first time I am using IFV tool. Whenever I try to run it it returns with the following errors:

Error at line 1 of /afs/ece.cmu.edu/support/cds/share/image/usr/cds/incisiv-12.10/tools/ifv/files/OVL/VHDL/cds.lib for /afs/ece.cmu.edu/support/cds/share/image/usr/cds/incisiv-12.10/tools/ifv/files/OVL/VHDL/ACCELLERA:

Invalid path

Error at line 1 of /afs/ece.cmu.edu/support/cds/share/image/usr/cds/incisiv12.10/tools/ifv/files/OVLACCELLERA/VERILOG/cdsovlverilog.lib for /afs/ece.cmu.edu/support/cds/share/image/usr/cds/incisiv-12.10/tools/ifv/files/OVLACCELLERA/VERILOG/OVLVERILOG:

Invalid path 

I have checked my file system and there is no ACCELLERA file. I don't understand why is it happening and how can I set it right. It will be really great if someone can direct me in the right direction.

 

Thanks, 

 

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delay of the get_next_item method

July 11, 2013, 7:52 am
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 Hi all

I have some question regarding the delay of get_next_item method.

 Is there an option to get result from get_next_item in "zero time" (no delay at all).

i have noticed that this method have an half cycle delay , is it all right ?

thanks in advance.

Moris.

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Assertions, assume - Not supported

July 12, 2013, 1:20 am
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Hello,

I've written few assertions in psl and have constrained them or asserted them in the tool.

When I go to the source browser containing these, and choose Display values, I get Not Supported.

Does this mean my assertions are not supported by the tool or the value display isnt supported?

Thanks. 

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FSM_NoDeadlock - Explored (IFV)

July 14, 2013, 9:06 pm
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Hello,

I've been using the IFV tool for quite sometime now and I notice that when I run FSM assertions under AFA, No deadlock assertions remain explored while the others pass easily. Is there anyway to improve this?

Thanks 

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Waveform in SimVision

July 15, 2013, 1:48 pm
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Hi! I am debugging my simulation traces with SimVision (both signals and transactions). SimVision groups signal names in sets of three signals by alternating black and dark gray backgrounds. Sometimes this makes very awkard the reading.

Is there are way to disable this option? Note that the background color option provided with the right click > color > background does not do exactly what I need: it changes the background of the waveform but not the one of the names.

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Simvision, the quickest way to know how many pulses one digital signal has?

October 13, 2010, 12:31 am
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 Is there any why to know how may pulses one digital signal has between some time in waveform? I think simvision could support some way, like expression or calculation, to count how many rising or falling edges in simulation.

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Zero-width pulse problem

July 24, 2013, 12:24 am
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I have a simulation that generate a zero-width pulse. There are two waveform file. One is vcd. Another one is shm. Both waveform was dump in same time. When i using Simvision to open both waveform, the VCD waveform file show the icon of zero-width pulse on waveform. But the SHM wavefrom file doesn't show it.

How can I set the Simvision showning the zero width icon?

 

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Not able to Merge Various coverage data base in ICCR tool.

July 25, 2013, 4:20 am
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Hi All,

I have 10 coverage data base inside the cov_work/scope/ ,i am using the following script to merge,loading and generating the data base.

merge -functional cov_work/scope/test *   -output all

load_test cov_work/scope/all

report_detail -both -nosource -nocompact * > Nc_Functional_Coverage_Report.txt

exit 

in the text file data base is not merging, but i can see in the merging in the gui mode.

I don't know what went wrong!!!

Wating for Reply...

Thanks

Himanshu 

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Vunits in PSL bind to spectre subckt

July 25, 2013, 10:04 am
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Hi,

Can anybody share how they are binding a PSL vunit with the spectre subckt.

 

Thanks

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Command Line option for Local Pulse Filtering

July 29, 2013, 11:30 pm
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Hi All,

 Goodmorning. I am trying  to find out an option for filtering pulse local to a module.

From docs, I see that, there are below command line options to filter pulse globally.

-pulse_e, -pulse_r, -pulse_int_e, -pulse_int_r

But globally enabling this option results in lot of warnings of type TRTIMING.  

Is there a COMMAND Line option for the same purpose but to enable this locally to some module.

 

From document, I see that  there is a PATHPULSE specparam which could be added in specify block of desired module.

But, a command line option was a better option.

 

Thanks
Roshan 

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Formal Verification with SystemVerilog and ifv

July 31, 2013, 4:35 am
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Hi,

i am trying to verify some SystemVerilogAssertions of a SV implementated communication network with incisif formal verifier, but the verification process takes a very long time and the computer crashes after 20 hours. The assertions test the whole network of sending and receiving. So is it possible to reduce the duration with some special commands (i use auto_dist as engine) or is the complexityan almost unsolveable problem?

 

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probe internal DUT signals

August 1, 2013, 6:42 am
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How to probe DUT(VHDL) internal signals for white box coverage??

Regards,

Pravin 

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Managing "delta" delays with VHDL/PSL

July 31, 2013, 6:41 am
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Hi,

We are using VHDL flavour PSL with a VHDL design, and are seeing assertion failures due to VHDL delta delays.

I read that SystemVerilog has solved this problem by checking all assertions in a new simulation phase. Is there any way of forcing ncsim to do this for a VHDL design?

Thanks,

Steven

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Enterprise Planner support system verilog / uvm ?

August 10, 2013, 4:28 am
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Does Enterprise planner supports importing of SV- UVM testbench? I am refering to Getting started document. It mentions of capability to import e testbench.

Ref

Incisive® Enterprise Planner
Getting Started
Product Version 12.1

Page 13

 

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who can help me? who can give me a download sit of ius10.2 or 11.1 or 11.2

August 15, 2013, 8:43 am
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recently, i am study the uvm but i have no the ius soft ,who can help me appreciated. if u can give a download sit

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SV Help ! how can dump the wave from class ?

August 18, 2013, 8:26 pm
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Hi, all

 Now I define a class ,and initiate it to a new class varible, I want to dump  some signals from it , how can I get that ? 

 

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clocking...endclocking block question in the ifv

August 26, 2013, 5:40 am
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Hi, All
 
I am a new beginner in the IFV, now I have a question of  how to implement the clocking...endclocking in IFV.
 
For the following code, I am intened to see the "din" in the waveform has a delay of 3ns to the "clk", I have never successed, could you tell me wheter the code has some issue(e.g., missed ports declaration) or list several key TCL commands for it?
 
I really appreciate you help!
 
Thanks,
Douglas 

 
 
 
`timescale 1ns/1ps
module  reg_s
    (
        clk,
        rst,
        din,
        dout
    );

    input                       rst;
    input                       clk;
    input                       din;

    output                      dout;

    reg                         dout;


    always @(posedge rst or posedge clk)
    begin
        if(rst == 1'b1)
        begin
            dout    <= 1'b0;
        end
        else
        begin
            dout    <= din;
        end
    end
endmodule


interface   reg_s_if(input clk);

    logic                       rst;
    logic                       din;
    logic                       dout;

    clocking cb @(posedge clk);
        default input #2ns output #3ns;
        input                 dout;
        outputdin;
 
proterty p_dout;
 ...
endproperty 
    endclocking
 
    ap_dout :assert  property(p_dout);
 
    modport drv_mp(clocking cb, output rst);

    modport dut_mp(input din, rst, output dout);

endinterface


module  tb;

    logic                       clk;
    
    initial
    begin
        clk     = 1'b0;
        forever
        begin
            #5ns;
            clk = ~clk;
        end
    end
    
    reg_s_if        u_reg_s_if(clk);

    reg_s           u_reg_s
                    (
                    .rst    (   u_reg_s_if.rst  ),
                    .clk    (   u_reg_s_if.clk  ),
                    .din    (   u_reg_s_if.din  ),
                    .dout   (   u_reg_s_if.dout )
                    );
                   
endmodule

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multiple uvm_package defination error

August 26, 2013, 7:03 am
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Hi everybody,
 
i have two different libraries named rtlwork and reggatwork and in both of them have an compiled UVM packages, one is used for normal rtl simulation and other is used for regression purpose.
 
but while i start simulation it shows an error as shown below, how can i get rid of this issue or is there a way to rename one of the package and how can i do this ??? 
 
import uvm_pkg::*;
               |
ncvlog: *E,MULTPK (/source_ovm/system_if_ovc/src/system_pkg.sv,58|15): Multiple (2) packages named "uvm_pkg" were found in the searched libraries: 
-> found verilog_package rtlwork.uvm_pkg:sv (VST)
-> found verilog_package reggatwork.uvm_pkg:sv (VST).
 
 
 
thanks in advance for your answers...
 
BR, Shravan 
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files required to use vams netlist

August 27, 2013, 10:54 am
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Hi All,

I am new to mixed singal verifcation. I want to run mixed signal verifcation using irun. I grabbed the verilog modules and replace some of verilog modules with veriog A and some with cadence schematic. Then I created the netlist.vams of whole design using ADE-L (AMS simulator).

Since digital team is using ncsim to verify funcationality, I would like to use the same environment and test benches by just replacing entire verilog modules to single netlist.vams file.

Can anybody provide me step by step help for this?

-Thanks in advance

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