vManager/IMC/Coverage: How to know what tests hit a specific coverpoint bin...
Hi,I am new to vManager / IMC, and am trying to analyze my set of tests by looking at the coverage report, but cannot find how to extract the test name that hit a specific coverpoint bin from the...
View ArticleIMC Merging: description of error/warning codes
Hi,I am trying to merge the functional coverage db form multiple tests, and realized that the IMC tool is giving many warning messages like this one (WEMCP2):*I,MERGL2: test1/Coverage:*W,WEMCP2:...
View ArticleEEnet Library Path
Hello,I'm trying to add EEnet Library with component list (capacitors, MOS, current sources...) into virtuoso for modelling purposes, but I cannot find it.I've looked into...
View Articlewaveform.wsf syntax manual
Hi,Is there any manual for editting the waveform.wsf file, that is created when saving user state in Verisium Debug?Up till now, I made some customizations, and when I saved, I saw how it is written,...
View ArticlePass variables to tcl script in Xcelium
Hello,I'm trying to pass a Variable through a command line input in the environment, so that my tcl script can take this for its startup initialization.xrun ... -command_that_sets_sets_a_variable...
View ArticleI observe following error when running xrun -sv
Design hierarchy summary: Instances Unique Modules: 2 2 Verilog packages: 0 1 Registers: 15 15 Scalar wires: 12 - Always blocks: 2 2 Initial blocks: 4 4 Pseudo assignments: 4 - Simulation timescale:...
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The simulation finished - Interactive session ending soon
Hello Everyone,I am trying to run my mixed signal testbench using cadence xcelium. When I try to open the terminal interactively, it says - 'This simulation finished ...'Please find below...
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SimVision: how to find all signals in the database matching a specific pattern?
Let's imagine I have a signal in my waveform database like test.top.channel_0.subChannel_A.mySignal.My design has many identical channels and each channel has many identical sub-channels, so the...
View ArticleSimple Assertion for Counter
Hi all, Question_1 : Assertion requirement : When Enable is HIGH, counter should be increment to previous clock cycle value, when Enable is LOW, counter should keep same value as previous cycle. Below...
View ArticleFunctional Coverage at SOC or Sub System Level
Hi All,At subsystem or SOC verification level,let’s say there are three IPs integrated : IP1, IP2 and IP3.Individually from block level verification, all IPs functional coverage is achieved 100%.IP1 FC...
View ArticleHow to eliminate DLCSMD errors in Xcelium's xrun
Hello,I am using cocotb in python to simulate SystemVerilog files and while there is no issue with other simulators such as modelsim, I came accross DLCSMD error in xrun. I have looked previous similar...
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