generate over a loop the same module with different parameter and maintain it in systemverilog UVM environment

Hi,

I've encountered in an issue that I'm trying to generate an interface with different parameter (DW) over a loop.

Therfore, I found that I've two problems;

1. How to generate the block (interface in my case) with a different parameter  (between each interface) over a loop?  I've tried generate block. 

2. How to maintain the data through config_db (set and get), virtual_interfaces, agents - same type with different parameters over the environment?

In case I've a chain of passive agents I don't like to duplicate the code so many times in my environment.

Regards,

Tomer