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How to effectively browse verilog source in Cadence

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Hi,

I know simvision can do source/load driver tracing but I believe it is more aimed at actual value tracing more than "browsing" through the code. I.e. I am looking for a Verdi style tracing, where it is easy to stop at module boundaries, the hierarchical panel on the left tells me where I am, etc. I find it really useful in seeing the bigger picture with regards as architecture, interconnections b/w modules and so on. In Simvision I just get lost when moving across boundaries, I could never find a way to make it work the way Verdi does. I am not sure I am using the right tool for the job?

Thanks


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