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Systemverilog SVA reporting in IUS: how to suppress failures caused by unfinished assertions?

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I'm sure this is a frequently asked question (FAQ)

When we turn on SVA in our simulations, some of our long-running concurrent assertions are triggering failures at the end of the simulation.  It appears the assertion triggered, but the simulaiton $finish before the assertion had a chance to complete (either vacuously-succeed, or normal succeed.)

When the assetoin-report is issued, these 'dangling' assertions are classified as failures.

Is there a way to change the report, or change the assertion-behavior so dangling-assertions are not reported as failures?


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