While running Jasper Gold CDC app, the constraint file contains commands to define virtual reset. What is the significance of this virtual reset. Also, we constrain ports with clocks in SDC file but not getting why ports are constrained wrt reset as well in JG using 'check_cdc' commands.

Hello,

Hi

Recently while I'm trying to fire regression for the collection of code coverage but I'm seeing some error saying DRM job removed only for two testcases (on running a standalone test with failing seed i could not see any failures, errors in simulation)so on checking log file i could see errors related to access issue from Backdoor, so I fixed the issue giving -access +rwc. Now after giving the access, increasing count number to the testcases and changing the queue to unlimit, i'm seeing the same following error. 

DRM job removed.
Job 2751721[3] removed by DRM. DRM Job status: TERMINATED
Debug aids:

Hello,

I'm trying to use vmanager in order to create a verification plan and then seeing it's coverage from regressions we run.

As for now, I use ximc in order to see the coverage. I click on the "Load Data" on the top left of the window, then navigate to the test directory, and then choose it and click load.

Inside that directory, there's a .ucd file.

Afterwards, I'm able to see the coverage, cover groups, percentage etc.

When trying to see the coverage in vManager, I'm trying to use the "Collect Runs" button.

From what I've read, I need to add a "write_metrics" argument to the run, and then in the same directory of the test I mentioned above, there's also a ".vsof" file.

Problem is, I don't see the coverage, it remains empty:

What am I doing wrong?

Thank you

Hello,

I'm running regressions to collect coverage, and I want to manage it with vManager and a vPlan.

Now, I'm running all kinds of tests, and each one fills ups their covergroups.

After doing a regression, I'm doing "collect runs".

Now let's say I have coverage for item_a and coverage for item_b.

item_a has 2 covergroups: item_a_cg1. item_a_cg2.

item_b has 3 covergroups: item_b_cg1, 2 and 3 likewise.

I did 1 regression that filled up item_a_cg1, item_b_cg2 and item_b_cg3 with some percentage.

Now I did another regression that filled up item_a_cg2 and item_b_cg1 and also item_b_cg3 again.

Now I want to merge these regressions so I'll the total percentage for each item, and each covergroup.

How can I do that?

I tried doing "export merge" but it didn't work as I intended.

Thanks

Hi All,

Is it possible to recompile the design or testbench file from Xcelium GUI? I know in Questa it's possible.

I mean should I close the GUI each time when I need to recompile the design or testbench files? Could not this be done from GUI?

Thanks!

Hallo

I have set a variable for the frequency of a input source, and than give a value in ade assembler.  After the simulatoin, i awared, that the simulator has rounded my value for the variable. 

My input value for the frequency variable is 107421875, 517578125, 771484375 and 4970703125 Hz. but in the plot view, all frequency are rounded, how can i avoid that to achieve a accurate value? thanks.

Why does simvision sometimes causes the desktop freezed?

Below are some details,

1. OS: CentOS 7.9

2. sivision version: XCELIUM/22.03.004

When the simvision causes the desktop freezed, I killed simvision process, then the desktop back to un-freezed.

Thanks.

Script Intent : To perform regression

I've written a script which has a list of all the test names. And each name is passed to makefile which invokes irun. 

Problem with script : instead of compiling only once, its compiling every time.

Here is the scirpt i've written.  So When I execute the script, two testcases are complied elaborated simulated twice. Now I want to complile only once using NCVLOG. But I'm unable to do so. Help me. and also how to do ncelab, ncsim? I know i should load the snapshot .

software version: INCISIVE15.20.086

---------------------------------------

script.tcsh

set list = (axi4_base_test axi4_base_test_1)
foreach item($list)
    make name=$item sim
end

Makefile

test_name=$(name)
include ../makefile

------------------------------

makefile

all :

sim :
@irun -clean -debug -uvm -sv +access+r +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=$(test_name) -l $(test_name).log -f /proj/users/chetan/4_axi_virtual/uvc/file.f

wave :
@simvision waves.shm &

log :
@gvim ./$(test_name).log 

------------------------------------------------------

I recently find that my Jaspergold 2021 always gets stuck after I run an 'analyze' command and can never proceed. I tried delete and reinstall but it does not work. The license should be good because it can checkout the license successfully after opening the app. Does anyone know how to solve this problem?

Hello, I have a problem with my verification process in which I couldn't find a solution to get around my problem.
I apologize, but I'm relatively new to this process.

In the study project I'm working on, I use a verilog testbench to perform my simulations with the xcelium simulator, for that, I make some hierarchical accesses of the instances contained in my submodules used in my testbench, for example:

In my "my_top_level", there is a kind of RAM, defined as:

 reg[31:0] RAM [0:100];

so i populate my ram with data via testbench doing:

module testbench;

 my_top_level my_top();
 reg [31:0] RAM_x [0:100];
 $readmemh("test.hex", RAM_x);
 for (i = 0; i < `L_RAM; i = i + 1)
   testbench.my_top.RAM[i] = RAM_x[i];

....

Worked well for my purpose. Also, I do this type of access to initialize some values to be able to run my simulation normally.

Example: testbench.my_top.processor.cycles = 0;

but when generating the netlist file there is something like:
  wire [31:0] \RAM[1] ;
  wire [31:0] \RAM[4] ;
  wire [31:0] \RAM[0] ;

Currently, I want to go ahead with a port-level simulation.
Because previously, I was making use of the non-synthesized "readmeh" instruction to be able to initialize my memory with my test instructions.

And I have no idea how to handle this kind of situation with the memory now unpacked. Would anyone have a direction on how to go about this? I'm very grateful!

It might be an unconventional approach but I need to pass some user defined arguments that have constrained value to a test and are of type real.

In the vsif file for regression I want to randomize those values in order for them to be different in each test.

Is there a way to do this? the only randomization I found in the manual is for integers used as seeds.

Thanks in advance

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Refuelling only once fuel hits the bottom of tank

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Hi, I wrote verification code (here two classes which extend from uvm_sequence_item and uvm_sequence). The $display in sequence illustrates only "ITEM: 000000000000000000000 or 0000000000000000" for 7 times (not 8). 

class item_incode extends uvm_sequence_item;
`uvm_object_utils(item_incode)
bit [20 : 0] in_code;
bit signed [15 : 0] in_data;

virtual function string convert2str();
return $sformatf("in_code = %b, in_data = %b", in_code, in_data);
endfunction

function new(string name = "item_incode");
super.new(name);
endfunction

constraint c_incode {
0 <= in_code [20 -: 3]; 3 >= in_code [20 -: 3];
0 <= in_code [17 -: 6]; 64 > in_code [17 -: 6];
0 <= in_code [11 -: 6]; 64 > in_code [11 -: 6];
0 <= in_code [5 -: 6]; 64 > in_code [5 -:6];
}
constraint c_indata {in_data inside {[-32767:32767]};}

endclass

class seq0 extends uvm_sequence # (item_incode);

`uvm_object_utils (seq0)

function new(string name = "seq0");
super.new(name);
endfunction

virtual task body();
repeat (8) begin
item_incode incode = item_incode::type_id::create("incode");;
start_item (incode);
incode.randomize();
$display("ITEM: %b or %b", incode.in_code, incode.in_data);
`uvm_info("SEQ", $sformatf("Generate new item: %s", incode.convert2str()), UVM_HIGH)
finish_item(incode);
end
`uvm_info("SEQ", $sformatf("Done generation of items"), UVM_LOW)
endtask

endclass

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hello sir, i have many signals like S_l1[25920:0]. 

so i use 'probe -create S_l1 -packed 25920' command.

my question is that 'is there any possible way to seperate this signal like S_l1[95:0], S_l1[191:96]  ...

because when i get that signal, i can only see entire signal like S_l1[25920:0]. 

thank you.

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I have some packages that live outside the top level testbench that drive some interfaces. I am trying to figure out how to add these signals into the waveform window. In Simvision, I can see all my packages and the signals from them, but they are in italics and say 'not probed':

How does one make these signals probed? Is there a file somewhere that tells the simulator what signals are probed? The simulation is run through a makefile script, here is a snippet from it. I tried adding the line that starts with 'probe' but I dont really know what I'm doing and this did not work:

if[!-d $(SIM_OUTPUT_DIR)]; then mkdir $(SIM_OUTPUT_DIR); fi; \
cd $(SIM_OUTPUT_DIR); \
find . -type f -maxdepth 1-delete; \
echo "Curent folder: "; pwd; \
irun -v200x -makelib rcf_lib ../../$(XSC_IP_DIR)/xsc_q7_neptec_ddvs_ntsc_ctrl_axi/src/hdl/constants_pkg.vhd -endlib \
-dumpstack -reflib xil_defaultlib $(IRUN_FILES) $(IRUN_SIM_OPT) $(IRUN_SIM_DEFINE_TC) $(IRUN_SIM_DEFINE_OPT) $(IRUN_CODE_COVERAGE_OPTIONS)-top $(TOP_LEVEL)-top glbl -logfile sim_log.log; \
probe -create -database waves::worklib.cpc_tools_pkg::cpc_tools -all -depth all

I may not have provided enough info to answer the quesiton, if so let me know what info is missing and I will try to answer it. Thanks in advance.

We are using Simvision for our waveform viewer, which I think it quite similar to ModelSim. I am trying to count all the edges on a signal between two time cursors. Normally this is very easy, I just click the count button and it tells me the number, but in my simulation I have a bunch of 'zero-width pulses' so its causing the count to be very high. In the screenshot, I am counting the edges on the signal coloured in magenta and you can see the count is 14, but I want it to count the actual 7 edges:

I am wondering if there is a way to not count the zero width pulses, maybe creating a signal with the expression calculator?

Thanks in advance!