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xmvlog warning: *W,DUPATR duplicate attribute name (trans)

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When I use xrun to do simulation, many warnings are reported as below:

-------------------------------------------------------------------------------

file: /proj/example/rtl/axi2local.v
(* covered_fsm, channel, is="IntCurState", os="IntNextState", trans="IDLE->IDLE", trans="IDLE->WAIT", trans="WAIT->WAIT", trans="WAIT->RSP", trans="RSP->IDLE", trans="RSP->RSP" *)
|
xmvlog: *W,DUPATR (/proj/example/rtl/axi2local.v,12669|87): duplicate attribute name (trans).

-------------------------------------------------------------------------------

It seems that xrun think it's not correct to use multiple "trans" attibute. But I think this is allowed in Verilog-2001 standard. I've seen this kind of code many times. Am I right?

Thanks a lot!


analog assert property doesn't show $display $error in both log file and SimVision console

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I want to know how to enable the $display/$error output defined in the assert property. I don't see it output in the log file.

Here is the system Verilog code:

##########start of sv code##################

module sv_as_micbiasamp_ibias5uA (

input real as_micbiasamp_ibias5uA,
output real as_micbias

);

localparam micbias_min5000 = 4500e-9;
localparam micbias_max5000 = 5500e-9;

// assert (as_micbiasamp_ibias5uA == 5e-6) $display ("OK. as_micbiasamp_ibias5uA equals 5uA");
wire micbias_ready = (as_micbiasamp_ibias5uA >= micbias_min5000) && (as_micbiasamp_ibias5uA <= micbias_max5000);

wire #10 up = micbias_ready;

property bias_current_micbias (tick, sig, lower, upper);
@(posedge tick) (lower < sig && sig < upper);
endproperty

CHK_MICBIAS_MIC_BIAS_5U: assert property(bias_current_micbias(up, as_micbiasamp_ibias5uA , 450e-8, 550e-8)) $display ("OK. current is within 5uA limit");
else $error ("MICBIAS error. Bias current micbias 5uA is not within limits");


always @*
if (up) begin
assign as_micbias = 1;
$display ("where this is displayed. OK");
end
else begin
assign as_micbias = 0;
$error ("where this is displayed. ERROR");
end
endmodule

########end of sv code###########

here is how the test bench looks like. I also have the ams config file and interface element setup properly for the net of Vnet_5uASource. The simulation can run correctly. 

I have test bench to report if the analog current into the systemverilog module is pithing 4.5uA or 5.5uA.

The $display and $error defined inside the property bias_current_micbias will not give any log output. But the $display and $error defined in the always @* block will correctly output to the log or SimVision console.

I want to see the below log displayed. Is there a setting will enable this feature?  

$display ("OK. current is within 5uA limit");  

$error ("MICBIAS error. Bias current micbias 5uA is not within limits");

##############example of $display and $error output ############

#############end of the output of $display and $error#################

community.cadence.com/.../test_5F00_AMS_5F00_log_5F00_error_5F00_assert_5F00_property.log

OVL assertions Library and INCISIVE152

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I am new to Cadence tools and the current project is using Incisive 152/Verilog/SV. I want to add SVA using the the OVL library, and I am looking for pointers on how to compile and use the std_ovl from Accelera in my TB. Are there any guides/documents that can help me.

Reading simulation time to a variable

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Hello,

Does anyone know if it is possible to read the running time and, then store it into a variable using TCL? 

Imagine that a simulation is running. Every time it is simulating the time moves, when it's not the time doesn't. With this, I would like to retrieve the real simulation time.

Thanks in advance.

Kind regards,

Pedro

how to merge coverage for each instances of the agents

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I am having a coverage class like this:

covergroup dst_addr_cov @(drv_dst_addr_event);
   dst_addr_cp: coverpoint cov_dst_addr { ignore_bins invalid_dst_addr = {19, 24, [27:59], 64, [65:$]};}
endgroup : dst_addr_cov

Instantiated for all the agents, how to see the merged coverage? hoping this will cover all signals for all agent instances.

AMS Advanced Testbench Reuse Flow: RAK

how to get time range of each waveform file?

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I use xrun to run a simulation and get a waveform directory -- "waveform.shm", which include a .dsn file and multiple .trn file. Each .trn wave file is 2GB size because I use "database -incsize 2G" to dump waveform. Now my question is, is there any way to get the time range of each .trn waveform file? For example:

0 ~ 1000ns             waveform.trn

1000ns ~ 2500ns   waveform-1.trn

2500ns ~ 4500ns   waveform-2.trn

This info is very useful because when debug waveform I don't want to open whole .shm waveform, it's too big. I want to open only specific time waveform. But I can't find this information after simulation is completed.

Instance is unresolved in module

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Hi,

I am using Altera Quartus 19.1 Standard Edition to generate a testbench system using qsys.

I am using the setup generated by it in to simulate using Xcelium. 

Using shell script , I am getting few following error 

xmelab: *E,CUVMUR (/home/videopath_tb/alt_vip_cl_cvo_191/sim/test_frame_videopath_alt_vip_cl_cvo_191_6d532fy.v,606|10): instance 'test_frame_videopath_tb.test_frame_videopath_inst.interlaced_cvo.cvo_core' of design unit 'alt_vip_cvo_core' is unresolved in 'test_frame_videopath_tb_alt_vip_cl_cvo_191.test_frame_videopath_alt_vip_cl_cvo_191_6d532fy:module'.
) video_out (
|
xmelab: *E,CUVMUR (/home/videopath_tb/alt_vip_cl_tpg_191/sim/test_frame_videopath_alt_vip_cl_tpg_191_na3yy5q.v,79|11): instance 'test_frame_videopath_tb.test_frame_videopath_inst.interlaced_tpg.video_out' of design unit 'alt_vip_video_output_bridge' is unresolved in 'test_frame_videopath_tb_alt_vip_cl_tpg_191.test_frame_videopath_alt_vip_cl_tpg_191_na3yy5q:module'.
) tpg_multi_scheduler_inst (
|
xmelab: *E,CUVMUR (/home/videopath_tb/alt_vip_tpg_multi_scheduler_191/sim/test_frame_videopath_alt_vip_tpg_multi_scheduler_191_esxktaq.sv,75|28): instance 'test_frame_videopath_tb.test_frame_videopath_inst.interlaced_tpg.scheduler.tpg_multi_scheduler_inst' of design unit 'alt_vip_tpg_multi_scheduler' is unresolved in 'test_frame_videopath_tb_alt_vip_tpg_multi_scheduler_191.test_frame_videopath_alt_vip_tpg_multi_scheduler_191_esxktaq:module'.
) core_0 (
|
xmelab: *E,CUVMUR (/home/videopath_tb/alt_vip_cl_tpg_191/sim/test_frame_videopath_alt_vip_cl_tpg_191_na3yy5q.v,138|8): instance 'test_frame_videopath_tb.test_frame_videopath_inst.interlaced_tpg.core_0' of design unit 'alt_vip_tpg_bars_alg_core' is unresolved in 'test_frame_videopath_tb_alt_vip_cl_tpg_191.test_frame_videopath_alt_vip_cl_tpg_191_na3yy5q:module'.
) mm_master (

Any help in finding solution will be appreciated.


How to create a counter of edges using the Simvision Waveform Viewer

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I am using Simvision for my debugs, I want to create a counter using either posedge or negedge of the signal.

I dont see any option to do so in Simvision, can someone let me know how to do this ?

Pad's to Allegro Translator 17.4

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Hello Forum,

I am trying to translate a old Pad's project to Allegro 17.4, looks like it is creating the netlist fine, but in the pads_in.log there is a message at the end,

ERROR: Subclass name SOLDERMASK_TOP not valid Allegro subcls for class ROUTE KEEPOUT. Quitting.
ERROR: Failed while writing the Allegro database.
Information: Object is empty, so CSet 1_16_17 renamed to DEFAULT

Warning: Default electrical CSets are not supported in Allegro PCB Editor.
Manually assign the ¡®DEFAULT¡¯ electrical cset to the objects.

Looking at the project.asc in Notepad++ but can't see what the issue is, any idea's would be greatly appreciated ! 

Thanks Much,

Mike Pollock.

report unused verilog packages

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Hi,

Is there any tool from Cadence that can report unused Verilog packages?

Often the import MyPackage::* statements are left at the top of a module declaration even though the code that was using them has been removed from the module. This causes unnecessary dependencies that may not be detected. So can I get a report of such unused packages from xmelab, JasperGold, Genus, or any other Cadence tool?

Thanks,

Max

how to save waveform signals to a file using tcl command?

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Hi.

In the manual of SimVision in one place I see that there a tcl command "waveform" that allows saving waveform using a command. But looks like this command does not exist, it is not in the list of SimVision Tcl commands. So my 2 questions:

1. is it possible to save wavefor using any tcl command

2. why is there "waveform" tcl command mentioned in manual (chapter "Managing Objects in the waveform Window"?

thx

Jacek

How to remove glitch from Asynchronous UVM TB?

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Hi All,

In our UVM_TB, driver is full of fork join and we drive addr, cmd and data. 

We are using cadence, xcelium tool. 

Enabled the event while probing for simvision to see the glitch:

probe  -default  -event

In the simulation, I see for every data that we write on data bus, there is a glitch and it is present thorugh out the simulation. 

Can you pleaes suggest the possible solutions to fix these glitches?

Thanns in advance,

[Xcelium]Simulation passed but getting the xmvlog E,UNSRFA error during compilation of the libraries

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Hi

I ran simulation of a design using Xcelium, Questasim and Riviera. For this design, all simulations passed but however for Xcelium, during compilation of an encrypted library file, the following error appear:

xmvlog: *E,UNSRFA: error within protected source code.
xmvlog: *E,UNSRFA: error within protected source code.

We didn't encounter this error while compiling that encrypted library file in Questasim and Riviera, all we got for these two simulators were only bunch of warnings.

I refer to Xcelium Message Error Guide and found out the following definition for E, UNSRFA:

"This task or function call actual argument cannot be connected to the specified formal reference argument because of the provided reason. Only entire variables, class properties or bit selects resolving to dynamic types can be passed. Default values for ref arguments must satisfy these same requirements."

My questions are:

1) Can someone explain more on this error by providing an example/scenario in which this error will occur?

2) Is it possible to downgrade this error to warning since similar kind of error didnt flag in other simulators that compiled the same encrypted library file?

Regards,

QN

internal exception Large VHDL Memory

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Hello,

I am using cadence Xcelium  for simulation and as I run the elaboration step, i am seeing the following message and the simulation process stops - 

xmelab: *W,LARGEM: Large VHDL memory (134217728 >= 2^25) declared (file: ahb_monitor.vhd, line: 62). You may hit system virtual memory exceeded issues.

xmelab: *F,INTERR: INTERNAL EXCEPTION
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: xmelab(64) 20.09-s006
HOSTNAME: rt-xicrh7-6
OPERATING SYSTEM: Linux 3.10.0-1160.41.1.el7.x86_64 #1 SMP Mon Aug 16 14:52:32 UTC 2021 x86_64
MESSAGE: cu_vhdl_sig_ptrblk_setdummysize(): Dummy sigsize setting botch
-----------------------------------------------------------------
csi-xmelab - CSI: Cadence Support Investigation, sending details to /projects/me158/me158aa/jps2rt/current/database_bosch_ip/gtm/sim_data/xmelab_27442.err
csi-xmelab - CSI: investigation complete, send /projects/me158/me158aa/jps2rt/current/database_bosch_ip/gtm/sim_data/xmelab_27442.err to Cadence Support
class AST_S_IF has parent of class AST_S_IF
xrun: *E,ELBERR: Error during elaboration (status 255), exiting.
TOOL: xrun(64) 20.09-s006: Exiting on Feb 09, 2022 at 11:11:24 CET (total: 00:01:35)
gmake: *** [makefile:151: compile_tb] Error 1

Any help on how to proceed would be appreciated.

Thank you.


different results from formal verification and simulation

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I wrote an a simple assertion and tried proving it with jasperGold fpv and simVision but they both gave opposite results. Can anyone help ?

assertion  --> clk_property: assert property ( @(posedge clk) disable iff(!rst) 1 |-> clk  ); 

 

Why does this assertion behave like this?

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Hi everyone!

I'm currently watching the lessons for the "SystemVerilog Assertions" course, and while doing the lab exercises I incurred in a behaviour which I can not understand. In lab 4, which requires to work on a SPI-like communication module, I need to cover a specific case in which the transaction's header (i.e. the first 8 bits of the transactions, which arrive LSB first starting from the clock cycle after the one in which the "frame" signal is asserted) does not correspond to any known sequence. Let's assume I write my code like this (not exactly what the lab asks for, but this way it's simpler to explain my issue):

localparam cfg = 8'b11001101;

...

sequence check_header(header);
     int i = 0;

    (serial == header[i], i++) [*8];
endsequence

...

cvg_ukn: assert property ( @(posedge clk iff !suspend) (
             $rose(frame) |=> not(check_header(cfg))
      )
);

 

What happens when I simulate is that the assertion becomes active when frame's rising is detected (the design is edge-negative, so the assertion detects it on the next rising clock edge), but then in the next cycle it becomes inactive! I do not understand: why does it become inactive? Is there something in the meaning of my consequent that I do not understand? Is there some tool configuration conflicting with what I wrote?

I now that the same property can be written in other ways (I know how to do that too), but I would really like to understand what's going on here.


(As side information, I'm working on Xcelium 21.03 and I run it with the command "xrun -64bit -SV -gui -access +rwc -svseed 1 -linedebug -abvrecordcoverall -input nc_input.tcl
spi.sv spi_test.sv top.sv" provided as a default script together with the labs files)

unable to route , showing DRC cursor

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Hi,

I am trying to connect a part to chassis ground and Allegro is not allowing me to make the connection for some reason. Here are some pictures to help:

The first picture indicates that there should be a connection between E4 and Chassis Ground. After I hover over it though it gives me the DRC cursor.

The second picture is after I try to route these 2 together.

I click on it anyway and the netlist trace is still there even though I tried to route the 2 together. Any ideas why this is happening?

I also got another unrelated question and hopefully It's ok to ask it along with this if not then please disregard.

This board is a 4 layer template and I am using it to create a single layer board. If I go to setup -> cross sections It looks like I can add layers on there but I cannot remove for some reason. I can get around this by only generating gerber files for the layer that I am using and disregarding the rest. Is there a way of turning this into a 1 layer board?

Note : this is PCB EDITOR version 17.2

Thanks all.

Neil Mustafa.

code coverage block analysis

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Hi team,

I am analysing code (block) coverage, I need help with the following;

LINE1: always @(cmd_enable)
LINE2: begin
LINE3: action1: assign
LINE4: action2: display
LINE5: end

in imc coverage report, I was able to see that LINE2 0% covered. How LINE2 will be covered. 

If LINE1 is not covered, means, then its is fine, the entire block will not get covered. 

But it was pointing out only at LINE2. 

Please suggest

Running "small environment" on specview

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Hi all,

I'm new in the functional verification "world" and I'm trying to create a small environment where i can test my code easily.

For that i wrote a simple code, where I generate a clock for my simulation.

Important to mention - I'm not connected to a DUT at this point because i want to create an easy "playground".

The problem is I'm receiving the next message:

"

*** Warning: ERR_TE_NOSIM: No simulator is attached.
Therefore, '@sim' and 'delay' temporal expressions will never occur.

"

The following is the code:

<'

extend sys {


event clk;
tcm_test() @clk is {
     print sys.time;
     wait [10]*cycle;
     print sys.time;
};


gen_clk() @sys.any is {
      while TRUE{
            message(LOW,"Wait delay");
            wait delay(4*(1 ns)); 
            emit clk;
            };
};

run() is also {
      print ("hello");
      start tcm_test();
};

run() is also {
      start gen_clk();
};


};

'>

Thank you for your help,

Nir

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