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NCLaunch VHDL compiler *F,DLUNNE error

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I'm trying to compile a VHDL code via NCLaunch. However, I keep getting the following error on the console

*F,DLUNNE: Can't find STANDARD at /vlsi/apps/cadence/ius/8.2HF015/tools/inca/files/STD.

There exists a folder named "standard" under the given path. There is no error in the VHDL code, either. During the cds.lib creation, I chose to add IEEE Pure libraries.

I can compile and elaborate Verilog code no problem, but VHDL compiler just doesn't work. I'm not sure what's happening. Please let me know if you need more information. Any help is appreciated.


Post synthesis simulation with XCELIUM - SDF

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hi,

due to technical problem i am running simulation through terminal. Therefore, I have a Verilog file, a test bench and i have also exported from Genus synthesized netlist and sdf file. Now, how can i annotate sdf in my post-synthesis simulation using XCELIUM while using command line?

thank you

Unable to Import .v files with `define using "Cadence Verilog In" tool

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Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);


inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify


endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);


inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify


endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Export a Breakpoint

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Hi all,

I was running a simulation with Xcelium in Simvision and I save few breakpoints.

I would like now to run another simulation (so from a different console) and loading one of the breakpoints of another simulation 

Is this possible? 

I try with the File -> Save Command Script and then sourcing the restore file but it is taking a lot of time

How to get product to license feature mapping information?

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When I run simulation with irun, it may use may license features. How can I know which feature(s) a product use? I get below message in cdnshelp:

-------------------------------------------------------------

Which Products Are in the License File?


One Cadence product can require more than one license (FEATURE). The product to feature mapping in the license file lists the licenses each product needs.


For example, if the license file lists these features for the NC-VHDL Simulator:


Product Name: Cadence(R) NC-VHDL Simulator
#
Type: Floating Exp Date: 31-jul-2006 Qty: 1
#
Feature: NC_VHDL_Simulator [Version: 9999.999]
#
Feature: Affirma_sim_analysis_env [Version: 9999.999]

-------------------------------------------------------------------

But, in my license file, I can't find such info. There is only "FEATURE" lines in my license file. How can I get product to feature mapping info?

Thanks!

Failed to inject fault at (ncsim)

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Hi,

I'm doing fault injection with ncsim and got stuck at the following (and not so useful) message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.


My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:4ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."


Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0


fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]


injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174


I already checked the NETs with simvision, so their paths are correct.


Any ideas?

PS: I know about Xcellium, however, I don't have it yet.

[IMC] Toggle coverage report

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Hi,

Is it possible to consider only 0->1 or 1->0 transition condition in toggle coverage report ?

I mean that I want to consider that a net is full covered if one of this transition is respected but not only if I have the both.

Thanks.

Nabil

ncsim: *E,FLTIGF: [FLT] Failed to inject fault at NET

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Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.


$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.


My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."


Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0


fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]


injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174


I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"


Any ideas are welcome.

Thank you in advance.


Portable Stmulus tool Perspec System Verifier

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Hi all,

I would please like to know if the Cadence tool for Portable Stimulus Standard namely Perspec System Verifier has an academic trial version. If not, the website says one can request a demo. But it seems this demo request page does not work. I can't submit my request. May be somone can please help me with this.

Thanks in advance

BR
Babar

VManager : Increase and Decrease the number of parallel runs in the on-going running sessions.

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While firing a regression that might span multiple working days, We need to increase and decrease the number of parallel runs to distribute license usages.

During working day hours, we would like to reduce the number of parallel runs and during nightly hours we should increase the parallel run.

Add a button to specview?

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I remember from long time ago, that there was some way of adding buttons to specview. I see a global sn_display object, that seems to have some API that might be used for things like that, but can't figure out how to use it. Maybe someone have a simple example somewhere? 

Can Cadence Incisive Enterprise Verifier be used for functional verification?

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I understand that Cadence Incisive Enterprise Verifier is for Assertion Based Verification, it has within it Incisive Enterprise Simulator which lets the tool generate testbench stimulus from assertions and thus gives dual benefit of formal and functional verification. My doubt is if I can use the tool exclusively for functional verification? That is I have a set of test benches that are already written, and I need to just simulate it just like we do in modelsim. Is it possible to do in Incisive Enterprise Verifier? If possible, please give insights on where I can refer on how to do that. I can't find details on this topic in the manual or user guide.

How do we extract a full path design from Scoreboard when there is a `uvm_error?

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Hi,

How do we extract a full path design from Scoreboard when there is a `uvm_error?

For example,

my_module has the following assigments:   (array of virtual interfaces, while each VF accepts data and data enable signals, with unique names)

assign my_module_internal_vif[#num].data_en = main_tb.<unique_name_per_each_signal>
assign my_module_internal_vif[#num].data = main_tb.<unique_name_per_each_signal>;

While there is a `uvm_error which happens in Scoreboard, I have the trans object (which is sent from the monitor). The trans has a field with instance number, but it doesn't monitor the signals themselves.

I have the #num or thre error.

My objective to to extract with a kind way, the full path design as a string and print it, given the number of the instance, i.e, when there is a `uvm_error, from trans[#num ], recognize  my_module_internal_vif[#num]  and then print the full path design which indicates which data enable was triggered and which data was compared.

Thanks for your help!

Excluding unused functions in JasperGold Superlint

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Hi,

Is there a way to avoid getting lint warnings from unused functions in JasperGold Superlint?

If I import a shared package that contains a function with linting errors, I don't want to see errors for this function unless I am using it.

Lint errors

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Jasper SuperLint  mesage pops to change the input of the top level module to register and register the input signals to increase controllability. how to resolve it


Does driver trace through system verilog interfaces ever work?

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Interfaces are great but it is so frustrating that driver tracing through them never works in Simvision.  Does this work for anybody or is it universally broken in Cadence simulators?

generate over a loop the same module with different parameter and maintain it in systemverilog UVM environment

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Hi,

I've encountered in an issue that I'm trying to generate an interface with different parameter (DW) over a loop.

Therfore, I found that I've two problems;

1. How to generate the block (interface in my case) with a different parameter  (between each interface) over a loop?  I've tried generate block. 

2. How to maintain the data through config_db (set and get), virtual_interfaces, agents - same type with different parameters over the environment?

In case I've a chain of passive agents I don't like to duplicate the code so many times in my environment.

Regards,

Tomer

[JasperGold] Behavioral Analysis - How to exercise it properly?

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Hi,

I'm running behavioral analysis in the apps RTL Development and Executable Specification from JasperGold, but the only results i obtained were:

Recipe Trace Lenght (old and new): N/A.

Assertion Violation: (Nothing).

Confirm VCD: (Nothing).

The steps performed were: 

  1. Run behavioral analysis;
  2. Set baseline;
  3. Update RTL;
  4. Run behavioral analysis again.

I'm trying to confirm vcds, check if assertions have failed, and update the recipe's trace lenght. 

Is there some step i'm missing?

 

Thank you,

Murilo

Analog circuit designing

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Why do we require high voltage swing at the output of line drivers?

e code coverage

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Is there some support for getting code coverage of my e files? I'm working in an environment where I suspect a lot of dead-code.

Thanks,

Avidan

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