I have ported my verification testbench from incisive 13.1 to 13.2.021 and getting stuck in simulation. Stimulation is stopping when it is detecting any interface (virtual) signal (say I want to drive vintf.clock or something like this). Do you have any idea why this is happening as I have not changed any other thing in my code and code was running fine on 13.1.
↧
Porting to new version getting stuck
↧
re: new version 14.10-s012 with assertions
Hi,
i have written a simple assertion to check for 2 pulse as
property(p1);
@(posedge clk)
($rose(in1) ##1 $fell(in1)) |-> ##[1:$] ($rose(out1) ##1 $fell(out1));
endproperty
Assuming at out1 is remains as 0(zero) through out the simulation. I should get assertion failure at the end of the simulation, but instead it is not giving messages (like vacuous success). But with the older version i am getting failure message. So help me out here.
Thanks
Srikanth M.
↧
↧
vr_ad register coverage for multiple instances of the same kind
I have a vr_ad model set up which has lists of registers of the same kind. The automatic coverage gives coverage on a per-kind basis, so I know that one of the registers has been read/written, and that all of the fields have been accessed, although not in which register. Is there an easy way to extend the coverage so you actually have it on a per-register basis and show that each individual register has been read/written? The only way I can see to do this is to cross the direction field and individual register fields with the list index in an extension to create my own coverage, as the per_instance coverage is already used to create the register coverage by kind.
↧
Using Cadnece SMV model checker
Dear all,
I was trying to download the SMV model checker from the website http://www.kenmcmil.com/smv.html. But, once I click the link given in the bottom of the page, its leading me to the main page of Cadence and not the download section of the Model checker.
Is there any other way to download the Cadence SMV tool (or equivalent student versions). I was using VIS Model checker from Colorado university, but the support is very poor.
Thanks a lot
↧
extend e language
Hello,
Does anyone have another idea on how to extend a unit or struct by two value of a field at a time? (macro'less I would prefer, micro'with I already have a solution)
type foo_t : [one, two, three];
unit foo_u {
foo_field : foo_t;
};
extend [one, two]'foo_field foo_u {
// enjoy here
};
Thanks,
Catalin
↧
↧
Class definition outside module and package
Hi,
I'm new to SV verfication and hence appreciate your help on this.
Usually I've seen SV class definitions inside a module / package . I remember having read before that class definitions cannot exist outside these, and as such cannot be compiled standalone.
But strangely, I've seen IUS14.1 successfully compiling a .sv file which contains only class definition. Do not see module/package constructs inside the file.
Am I missing something in my understanding? Thanks for your suggestions and help in advance.
Regards
Kishore
↧
Back annotating the SDF data to a verilog nestlist in VHDL testbench
Dear experts
I am using VHDL as description language for my RTL development including testbenches and Cadence RC for synthesis. The synthesized netlist is in veilog and I would like to use it within the VHDL testbench to perform GLS. The standard cell models are available in verilog as well. I want to back annotate the timing information in SDF file generated during synthesis. Could someone guide me on the steps to be followed for the same. I use ncsim for simulation environment.
Thanks and regards
Venkat
↧
Practical guide to integrate Specman with a ISS
Hello,
I recently developed an Instruction Set Simulator using an Architecture Description Language called ArchC.
My plan is to port this ISS into Cadence's tools for further Embedded Software Verification.
It seems a good idea, however I'm facing serious problems to integrate the ISS with Specman.
I was wondering if is there a practical guide, or examples with an ISS written in SystemC?
I tried to use the IVB to create the project files, but it seems so complicated, I'm looking for a simple example
that uses an ISS in SystemC. (All the examples in the documentation either use Verilog or Host code Execution)
Thank you.
↧
Understanding expression coverage
reg marker;
always@(posedge clk or negedge rst_n)
if ( ~rst_n )
marker <= 0;
else
if ( push_and_pushed )
if ( ( ( framecount==0 ) && ( f_wdata[4:0] == 0 ) ) ||
( ( framecount >0 ) && ( framecount==sample0 ) ) )
marker <= f_wdata;
And expression coverage tells me this:
I do not understand what situation it complains about.
T1=1 suggests framecount non-zero
T4=0 suggests framecount to be zero at the same time
What do I misinterpret here?
↧
↧
using sys.realtime
Hi,
Can you please explain the influence of the `timescale and precision on sys.time and sys.realtime.
In specman e language reference it says that:
* "A field of type real named sys.realtime, which can hold a more precise simulator time than sys.time."
* "The precision of the timescale scales the precision of sys.realtime."
For example, I'm using 1ns/10ps but when I try to print sys.time and sys.realtime the same value is printed.
my code does the following:
event xx is fall ('hdl_path')@sim;
on xx {
print sys.time;
print sys.realtime;
};
In addition using delay() with t : real where t = 1.5 doesn't work.
So can you please clarify the difference between the two and how to use them correctly?
Thanks!
Yael
↧
UVM_ML (SystemC + SystemVerilog TB)
Hi,
Question about architecture of SystemC UVM + SystemVerilog UVM.
Can those two approaches be mixed?
1. Can SystemC uvm_components exist within SystemVerilog's UVM tree hierarchy?
In other words - can SystemVerilog instantiate SystemC class in itself?
2. If SystemVerilog UVM cannot instantiate in itself UVM components of SYstemC - it will mean that the testbench will have multiple tops (one top for SC, the other for SV), is it correct?
Many thanks
Witold Kaczurba
↧
memory profile using simvision simulator
Hi ,
Is there any way to check what portion of code takes what amount (or percentage ) of memory in simulation using simvision?
I used "-profile" option which gives me the idea how many hits one type of code gets. I want to see the memory usuage of different modules/ areas/ structures.
Thanks
↧
Post-layout simulation eval error
Hello All,
I have designed a simple circuit and extracted the DSPF file. Now I am using the DSPF file as input to run po-layout simulation but I am confused for the measurement statements,
in the DSPF file my Instance is
XXMEM_CELL1|CC0 XMEM_CELL1|CC0:pos XMEM_CELL1|CC0:neg CC0:SUB egncap L=0.25u W=1u nf=1 nrep=1 setres=-2 setind=-2 m=1
so If I want to measure the voltage at Positive terminal of this CC0 How I would write the O/p Statement ?? I tried selecting the net on design but the simulation gives me eval error,
I am using Spectre simulator with Version 14.1.0.576.isr7 64bit -- 28 Apr 2015.
P.S: this Mem_Cell1 is the instance in my top level and there is no o/p pin to it so I need to divein this Instance to select the Net or Pin from it. I am getting results for the PIN that are available in Top level design. For Schematic simulation I can slecet any net and simulate but for post layout simulation it fails.
Any help or hint on this ?
Thanks
↧
↧
Broken Coverage Definition in VPLAN
Hi
I have a VPLAN, and I have a set of coverage data. I have mapped my functional coverpoints from the coverage data to the VPLAN.
When I view the VPLAN (in eplanner) everything is mapped. When I view the coverage data (using IMC) I see all my covergroups hit.
BUT when I look t the coverage results in the VPLAN view a number of sections (not all) are showing errors (no checks) and are reporting 'Broken Coverage Definition'
Can anyone tell me what I might have done wrong ?
Regards
Tim
↧
ncsim: *E,TRSRANGE: range constraint violation (signal update).
Hello,
I am able to run the simulation without any problems on modelsim. The same testbench on ncsim gives me the error after the simulation starts and runs for about 5us.
Can someone please help me with this? My assumption is that it points to the following two lines of code:
psi5_s <= (ano => ANALOG_Z, ani => psi5_i_s);
psi5_o_s <= psi5_s.ano;
Any help will be great.
Best regards,
Vidya.
↧
$nc_force never raises an error in ncsim
Hello Everyone,
I am using nc_force to raise the signals in my testbench. I am using a path which never exists like this:
$nc_force("blablabala", 5.0, "verbose");
This never raises an ever during execution or provides any verbose. Where am I doing something wrong?
Any support on this is greatly appreciated. Thank you very much.
Regards,
Vidya.
↧
Redirect Spectre results to buffer
I have written a program which reads in a text formatted tran.tran Spectre results file, analyzes the results, then modifies component parameters within input.scs in attempt to improve circuit behaviour. it does this repeatedly for many iterations.
The problem I am having is that the tran.tran file can be very large, making it time consuming to write and read a result file on the disk. I would like to know if it is possible to redirect Spectre's output to a memory buffer which my program could read from, avoiding the overhead of hard disk IO.
↧
↧
Irun not accepted systemverilog macro
I try to define macro
`define MY_MACRO(par1, par2 = 0)If i use irun version 08, in console outputs error:
`define MY_MACRO(par1, par2=0) | ncvlog: *E,EXPRPP (trunk/testbench/include/test_macro.svh,6|27): expecting a right parenthesis to close the formal arguments to a macro [16.3.1(IEEE)].
If I use irun version 11 everything is ok.
irun version 8 is not supported constructions with default arguments values in macro?
↧
Bind interface UVM issue
Hi everyone
I use bind to connect to a internal interface defined on module top_tb:
bind dut.wt_clock_mux_glitch_free wt_clock_mux_if wt_clk_mux_if0(
.clk1(clk1),
.clk2(clk2),
.rst_b(rst_b),
.wt_clk_sel(wt_clk_sel_r),
.wclk(wclk)
);
but I got an error:
ncelab: *E,CUVHNF (./wdt_top_tb.sv,48|64): Hierarchical name component lookup failed at 'dut.wt_clock_mux_glitch_free'.
irun: *E,ELBERR: Error during elaboration (status 1), exiting.
I need some advices,
Thank you!
↧
Looking for the values of UVM register model in the simulation
Hello all,
I have implented UVM register model and trying to write to and read values from the register model. I would like to see the register model content in incisive ncsim simulation. I dont see a register model instantiated in the desing browser nor can i find a way to add them to the wayform window.
Your views are appreciated.
Thank you.
Best regards,
Vidya.
↧