Why is the error message generated in my simulation run. I've run the simulation for a while, this is the first time I saw this message pop up.
Thanks for your input.
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ncsim: *E,DENOTS: No time specification given for value: after
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NCVHDL simulation error
Sir, am getting this error when trying to elaborate the design
[root@localhost simulation]# ncelab WORK.trial:trial_rtl
ncelab: 10.20-p008: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
ncelab: *W,DLMLUP: Unable to access modified marker for library 'std'.
file: /cad/INCISIV102_lnx86/tools/inca/files/STD/.cdsvmod (Permission denied).
ncelab: *W,DLMLUP: Unable to access modified marker for library 'synopsys'.
file: /cad/INCISIV102_lnx86/tools/inca/files/SYNOPSYS/.cdsvmod (Permission denied).
ncelab: *W,DLMLUP: Unable to access modified marker for library 'ieee'.
file: /cad/INCISIV102_lnx86/tools/inca/files/IEEE/.cdsvmod (Permission denied).
ncvhdl_cg: *W,DLMLUP: Unable to access modified marker for library 'ieee'.
file: /cad/INCISIV102_lnx86/tools/inca/files/IEEE/.cdsvmod (Permission denied).
ncvhdl_cg: *W,DLMLUP: Unable to access modified marker for library 'std'.
file: /cad/INCISIV102_lnx86/tools/inca/files/STD/.cdsvmod (Permission denied).
ncvhdl_cg: *W,DLMLUP: Unable to access modified marker for library 'synopsys'.
file: /cad/INCISIV102_lnx86/tools/inca/files/SYNOPSYS/.cdsvmod (Permission denied).
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Connecting VHDL port to system verilog interface definition in UVM
I have a package definition in VHDL which contains the user defined array type which is the output of my DUT.The definition is as below:
TYPE loop_reg_ty IS RECORD
loop_index_value : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
loop_counter : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
loop_end_flag : std_logic;
END RECORD;
TYPE loop_array_ty is array (MAX_NO_OF_LOOPS-1 downto 0) of std_logic_vector(REG_BITWIDTH-1 downto 0);
I read in other posts that cadence doesn't support importing the package into system verilog environment and hence i am trying to define the similar structure in system verilog environment as below :
typedef struct packed { bit [REG_BITWIDTH-1:0] loop_index_value; bit [REG_BITWIDTH-1:0] loop_counter; bit loop_end_flag; } raccu_loop_reg_ty; typedef loop_reg_ty [MAX_NO_OF_RACCU_LOOPS-1:0] loop_array_ty;But during elaboration i am getting the error as below :
ncelab: *E,CFMPTC : VHDL port type is not compatible with Verilog.
Please let me know the possible work around solution for this.
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Error in Elaboration in UVM environment
I am trying to test the VHDL DUT in UVM environment and as i can see using the libverbose all the units are properly resolved when i used irun and it shows error in elaboration as below :
irun: *E,ELBERR: Error during elaboration (status 1), exiting.
I am not able to see any other error messages.
Can you please help me how i can further debug to know the exact reason for the error ?
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Disabling single signals in expression coverage?
I am running expression coverage on a design. There are many ATPG multiplexers implemented in RTL, such as
wire signal = aptg_mode ? something : something_else;
Expression coverage complains that, since atpg_mode is always 0 in RTL simulations, the ternary expression is only 50% tested. Is there something I can do about it? Like, a pragma that tells the coverage scoring that atpg_mode is considered to be constant '0'?
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How to exclude a register or bit in IMC by certain value
Hi,
I'm using IMC to do the coverage.
I have successfully exclude instance and module, both in ccf file and manually by hand; also I have found the toggle view, which can exclude a certain bit's, rise or fall.
However I was look for the way to exclude by certain value, does anyone know about it?
For example, I have a 3-bit register A. During coverage, I want to exclude it when it was 000, 010, 110, 111. Toggle exclusion seems helpless at this point.
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Merge conflict with iccr
Hi,
I'm wondering if there is a bkm to resolve a merge conflict.
I have been running iccr merge just fine until I had to fix one of the coverpoints. Now I'm getting a coverpoint not merged - description differs.
Thanks,
-Victor
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About timing precision of sdf file simulated in ncsim
Hello Every,
Thank you for your kindness in advance.Here is my problem
I find my ncsim can only simualte the sdf file in precision of 10ps （round to 10ps）
For exampe，This is a simple BUF sdf information:
[syntax=verilog](CELL
(CELLTYPE "BUFCLKHD30X")
(INSTANCE U10)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.263:0.266:0.266) (0.257:0.259:0.259))
)
)
)[/syntax]
When I observe the timing sequence in simvision window, I found the simulator will round the IOPATH delay to 270ps when Z transfering from 0 to 1 because of the changing of A.
In my sdf file the Timescale (unit) is 1 ns. And in my testbench is 1ns/1ps. And according the tools documentation from cadence, the default timing precision of sdf elaberating/compiling is 1fs. I think that means we do not need to set any precision relating compiler option (like sdf_precision 1ps) in ma case. (BTW, I have tried such complier option, but help nothing).
How can I watch/oberseve a delay of 266ps from my simvision waveform window？ Mnay thanks.!
My ncsim version is IES 2012, I thnik it was "latest" enough.
Many thanks.
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set/reset inversion
Hi all,
Any condition a DFF/DLAT will be remodel to BUF/INV ?
I get a message that LEC remodel due to set/reset inversion.
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failed to generate .saif using "irun" command -> "Unrecognized system task or function"
Hi,
I failed to generate .saif using "irun" command
All my function i tried to use: $read_rtl_saif, $set_toggle_region, $toggle_start, $toggle_stop, $toggle_report are being warned as "Unrecognized system task or function" by NCSIm.
Anyone may suggest why is this happening?
Thanks.
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merging code coverage with different .ccf
Hi,
Is it possible to merge two code coverage DB's of same RTL but with different coverage configuration files (ccf).
thanks in advance
marsun
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Facing issue while running ncelab step after ncverilog
Hello,
I am facing this issue while running ncelab step. I have ran ncverilog and it passed .
I am running it from the command line and i am getting the following error
DEFINE lib_std /home/np959/CADENV_HOME/worklib/libraries/slow_vdd1v2_basicCells.lib
|
ncelab: *W,DLCPTH (./cds.lib,6): cds.lib Invalid path '/home/np959/CADENV_HOME/worklib/libraries/slow_vdd1v2_basicCells.lib' (cds.lib command ignored).
ncelab: *E,NOUNIT: Unable to find a unit named 'worklib.count16' in the libraries.
I am running the following command :
ncelab worklib.count16
The verilog file - count16.v and the testbench name is count16_tb.v .
Please let me know where i am going wrong. and incase if someone can list down the commands in the order , may be i am going through wrong steps.
Regards
Tanvi
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Spice Model for VPWL_F_RE_FOREVER
I want to use VPWL_F_RE_FOREVER in a circuit but I am not able to find the pspice models for source library. Please help me in suggesting how can I get the models or an alternative solution to the problem.
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Help with Optimizer (model parameters)
Greetings.
Is there some way to use Optimizer (Orcad PSpice 16.5) in order to optimize model parameters (in the actual case, N and IS of a diode) and achieve fitting of the experimental data?
I read on the internet that it should be possible, but I was not able to make Optimizer recognize the two model parameters as optimizing parameters.
Thanks
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Simulation error: "Line too long. Limit is 132 characters."
I'm simulating a 3rd-party Spice model of a transistor using OrCAD PSpice. After I hit run, it starts to generate a .cir file which is when the following error shows up:
Line too long. Limit is 132 characters.
By replacing the transistor model with a simpler one, the simulation goes well, so the error is somehow related to the transistor model.
What I don't understand is that the .cir file is generated by the software. Why the software generates some code which doesn't follow its own rule? I mean, it could split a long expression into several lines to avoid the error. Indeed, what I care about is how to solve the problem. The complete output file of the simulation is in the following. Any suggestions or comments would be appreciated.
**** 02/06/15 15:12:39 ****** PSpice 16.5.0 (April 2011) ****** ID# 0 ********
** Profile: "SCHEMATIC1-sim" [ C:\Temp\02MyProject2\Pspice\inverter3_2\inverter1-pspicefiles\schematic1\sim.sim ]
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "sim.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Cadence\SPB_16.5\tools\PSpice\PSpice.ini file:
.lib "C:\Cadence\SPB_16.5\tools\pspice\UserLib\00_UPDATED_Infineon_Simulation Model_PSpice_CoolMOSO_C7_650V_UPDATED.lib"
.lib "C:\Temp\02MyProject2\ARCP\Pspice\GaN device\GaN FET\EPC2010\EPC2010_V102_PSPICE.lib"
.lib "nom.lib"
*Analysis directives:
.TRAN 0 20us 0
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source INVERTER1
V_V2 G1 OUT
+PULSE 0 15 0 0 0 9.5us 20us
V_V5 G2 0
+PULSE 0 15 10us 0 0 9.5us 20us
V_V4 N04438 0 DC 5
R_RG1 G1 N04464 10
I_I1 OUT 0 DC 0Adc
R_RG G2 N04426 10
X_U5 N04438 N04464 OUT IPW65R019C7_L1 PARAMS: DVTH=0 DRDSON=0
X_U6 OUT N04426 0 IPW65R019C7_L1 PARAMS: DVTH=0 DRDSON=0
**** RESUMING sim.cir ****
.END
.PARAM r2={(fpar1*SQRT(0.4)-fpar4)*Inn*r0}
.PARAM Rlim={(r1+2*r2*Rmax-SQRT(r1**2+4*r2))/(2*r2)}
.PARAM dRd={fpar18/a+if(dVth==0,limit(dR,0,1)*max(Rlim-fpar18/a-Rs-Rp,0),0)}
.PARAM bm={fpar4/((1/gmin-Rs)**2*Inn*a*(fpar21/fpar20)**fpar29)}
.PARAM bet={fpar14+(fpar14-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)}
.PARAM dC1={1+dCmax*limit(dC,0,1)}
.PARAM x0={(fpar35-fpar36)/fpar37} x1={fpar35/fpar37} dx={x1-x0} y1={(fpar40*a+fpar41)*dC1}
.PARAM a0={(fpar49-fpar50)/fpar51} a1={fpar49/fpar51} da={a1-a0}
*.PARAM aqc80={a*fpar49*dC1}
.PARAM aqc81={a*fpar50*dC1}
*.PARAM aqc82={a*fpar51*dC1}
.PARAM Cox1={fpar38*a*dC1}
.PARAM y0={fpar36*a*dC1}
.PARAM C0={fpar42*a*dC1}
.PARAM C1={fpar43*a*dC1}
.PARAM C2={fpar45*a*dC1}
.PARAM C3={fpar52*a*dC1}
.PARAM Cgs0={(fpar34+fpar33*a)*dC1}
.PARAM dRdi={fpar24/a}
.PARAM y2={fpar47*a*dC1}
.FUNC QCdg1(x) {y0*min(x,x1)+y1*max(x-x1,0)+y2/2*max(0, x-fpar48)**2+(y0-y1)*((limit(x,x0,x1)-x0)**3/(dx*dx)*((limit(x,x0,x1)-x0)/(2*
$
ERROR(ORPSIM-16366): Line too long. Limit is 132 characters.
.FUNC QCds1(x) {aqc81*min(x,a1)+aqc81*((limit(x,a0,a1)-a0)**3/(da*da)*((limit(x,a0,a1)-a0)/(2*da)-1))}
.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))}
.FUNC Ig(Uds,T,p,Uee,cc) {bet*(fpar21/T)**fpar29*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)}
.FUNC J(d,g,T,da,s)
+ {a*(s*((Ig(da,T,(fpar15+(fpar16+fpar17*T)*T)*fpar3*T,g-Vth+fpar6*(T-fpar20),fpar4)+1*exp(min(fpar12+(d-fpar13-fpar10*(T-fpar20))/fp
$
ERROR(ORPSIM-16366): Line too long. Limit is 132 characters.
.PARAM dRd {fpar18/a+if(dVth==0,limit(dR,0,1)*max(Rlim-fpar18/a-Rs-Rp,0),
+ 0)}
.PARAM bm {fpar4/((1/gmin-Rs)**2*Inn*a*(fpar21/fpar20)**fpar29)}
.PARAM bet {fpar14+(fpar14-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),
+ 0)}
.PARAM dC1 {1+dCmax*limit(dC,0,1)}
.PARAM x0 {(fpar35-fpar36)/fpar37} x1 {fpar35/fpar37} dx {x1-x0} y1 {(fpar40*a+fpar41)*dC1}
.PARAM a0 {(fpar49-fpar50)/fpar51} a1 {fpar49/fpar51} da {a1-a0}
.PARAM aqc81 {a*fpar50*dC1}
.PARAM Cox1 {fpar38*a*dC1}
.PARAM y0 {fpar36*a*dC1}
.PARAM C0 {fpar42*a*dC1}
.PARAM C1 {fpar43*a*dC1}
.PARAM C2 {fpar45*a*dC1}
.PARAM C3 {fpar52*a*dC1}
.PARAM Cgs0 {(fpar34+fpar33*a)*dC1}
.PARAM dRdi {fpar24/a}
.PARAM y2 {fpar47*a*dC1}
.FUNC QCds1(x) {aqc81*min(x,a1)+aqc81*((limit(x,a0,a1)-a0)**3/(da*da)*(
+ (limit(x,a0,a1)-a0)/(2*da)-1))}
.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))}
.FUNC Ig(Uds,T,p,Uee,cc) {bet*(fpar21/T)**fpar29*I0(Uee,p,min(2*p,p+cc*Uds),
+ min(Uds,Uee/(2*cc)),cc)}
.FUNC J(d,g,T,da,s)
-------------------$
ERROR(ORPSIM-16270): No .FUNC definition
.PARAM dRd {fpar18/a+if(dVth==0,limit(dR,0,1)*max(Rlim-fpar18/a-Rs-Rp,0),
+ 0)}
.PARAM bm {fpar4/((1/gmin-Rs)**2*Inn*a*(fpar21/fpar20)**fpar29)}
.PARAM bet {fpar14+(fpar14-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),
+ 0)}
.PARAM dC1 {1+dCmax*limit(dC,0,1)}
.PARAM x0 {(fpar35-fpar36)/fpar37} x1 {fpar35/fpar37} dx {x1-x0} y1 {(fpar40*a+fpar41)*dC1}
.PARAM a0 {(fpar49-fpar50)/fpar51} a1 {fpar49/fpar51} da {a1-a0}
.PARAM aqc81 {a*fpar50*dC1}
.PARAM Cox1 {fpar38*a*dC1}
.PARAM y0 {fpar36*a*dC1}
.PARAM C0 {fpar42*a*dC1}
.PARAM C1 {fpar43*a*dC1}
.PARAM C2 {fpar45*a*dC1}
.PARAM C3 {fpar52*a*dC1}
.PARAM Cgs0 {(fpar34+fpar33*a)*dC1}
.PARAM dRdi {fpar24/a}
.PARAM y2 {fpar47*a*dC1}
.FUNC QCds1(x) {aqc81*min(x,a1)+aqc81*((limit(x,a0,a1)-a0)**3/(da*da)*(
+ (limit(x,a0,a1)-a0)/(2*da)-1))}
.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))}
.FUNC Ig(Uds,T,p,Uee,cc) {bet*(fpar21/T)**fpar29*I0(Uee,p,min(2*p,p+cc*Uds),
+ min(Uds,Uee/(2*cc)),cc)}
.FUNC J(d,g,T,da,s)
-------------------$
ERROR(ORPSIM-16270): No .FUNC definition
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Getting SWIFT internal error:bad call of realloc:Failed to allocate block
I am using following commands to save a checkpoint and later on wanted to restore it in order to create a snapshot,Commands used are
ncsim>stop -object test.active
ncsim>run
ncsim>run -clean
ncsim>save -overwrite worklib.first_snap
ncsim>run 2000ns
ncsim>restore first_snap
After the "save -overwrite worklib.first_snap" command got the below mentioned error.
Message! [SDI/Verilog]
SDI/Verilog does not support save - no SDI information will be saved.
Current simulation time = 0
"/icfe_tools/incisv12.10.s012.hotfix/tools/uvm/uvm_lib/additions/sv/cdns_recording.svh", 75: $sdi_create_fiber(name,t,scope);
SWIFT internal error: bad call to realloc: Failed to allocate block: Size 188978564442, SaveRestore.c, Line 1340
File 'SaveRestore.c', Line 1340
Can anyone please help in getting this issue resolved or is there any other alternative way for saving and restoring checkpoint.
Thanks,
Usha
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How to correctly run specman with ncsim ?
Hello,
I started to experiment with VHDL+Specman. I wrote some code and now I want to simulate VHDL and E together. I use following command to run the simulation:
specview ncsim -gui -cdslib /proj/specman_first_xortest/cds.lib -logfile ncsim.log -errormax 15 -status worklib.tb_xortest:tb
But I am getting following messages:
*Novas* Loading libsscore_ius121.so
*Novas* libsscore_ius121.so: cannot open shared object file: No such file or directory
*Novas* Cannot load libsscore_ius121.so from following LD_LIBRARY_PATH
/cad/cds/incisiv/incisiv12.20.011/tools/lib/64bit:/cad/cds/incisiv/incisiv12.20.011/tools/lib:/cad/cliosoft/sos/sos_6.31.p2/
lib:/cad/cliosoft/sos/sos_6.31.p2/lib/64bit:/custom/tools/apps/release5/ONpli/64bit:/custom/tools/apps/release5/ONpli/32bit:
/site/custom/tools/apps/gtkextra/lib:/custom/tools/it/rtda/2013.09/linux64/lib:/cad/cds/incisiv/incisiv12.20.011/specman/lin
ux64
*Novas* Failed to load FSDB dumper.
-------------------------------------
Relinquished control to SimVision...
Failed to register epi test phase change update callback.
Failed to register epi unit tree update callback.
ncsim>
ncsim> source /cad/cds/incisiv/incisiv12.20.011/tools/inca/files/ncsimrc
What is going wrong and what can I do to correctly run the simulation ?
↧
↧
Getting ERROR when I try to save and restore waveform.
When I try to save a checkpoint, so that I can restore it later.
But when I try the below command,
ncsim> save checkpoint_1
I am getting the below error,
Message! [SDI/Verilog]
SDI/Verilog does not support save - no SDI information will be saved.
Current simulation time = 0
"/tools/cadence/INCISIV121/tools/uvm/uvm_lib/additions/sv/cdns_recording.svh", 75: $sdi_create_fiber(name,t,scope);
SWIFT internal error: bad call to realloc: Failed to allocate block: Size 188978564442, SaveRestore.c, Line 1340
File 'SaveRestore.c', Line 1340
Can anyone please help me resolve this issue.
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Idea of scoreboard checking in Specman needed
Hello all,
I have DUT which generates certain combination on two outputs. My idea is to use keyed list, somehow fill the values in and somehow implement the coverage on that keyed list.
struct dut_output {
out1: uint(bits:6);
out2 : uint(bits:6);
};
struct scoreboard_s {
!dut_out : list (key:out1) of dut_output;
// fill the scoreboard list
fill_scboard () is {
dut_out.add( {2;15}); // how to do that correctly here ???
dut_out.add( {5;11}); // how to do that correctly here ???
dut_out.add( {7;5}); // how to do that correctly here ???
};
// check outputs
check_outputs( res:dut_output) is {
var temp_out : dut_output = dut_out.key(res.out1);
if (temp_out.out2 != res.out2) {
dut_error("Wrong OUT2 value!");
};
};
};
How do you fill the scoreboard ? And how to do the coverage is this case ?
Thank you for ideas.
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SystemC-AMS support
Is SystemC-AMS supported by Incisive tools?
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