Hi, I wrote verification code (here two classes which extend from uvm_sequence_item and uvm_sequence). The $display in sequence illustrates only "ITEM: 000000000000000000000 or 0000000000000000" for 7 times (not 8).
class item_incode extends uvm_sequence_item;
`uvm_object_utils(item_incode)
bit [20 : 0] in_code;
bit signed [15 : 0] in_data;
virtual function string convert2str();
return $sformatf("in_code = %b, in_data = %b", in_code, in_data);
endfunction
function new(string name = "item_incode");
super.new(name);
endfunction
constraint c_incode {
0 <= in_code [20 -: 3]; 3 >= in_code [20 -: 3];
0 <= in_code [17 -: 6]; 64 > in_code [17 -: 6];
0 <= in_code [11 -: 6]; 64 > in_code [11 -: 6];
0 <= in_code [5 -: 6]; 64 > in_code [5 -:6];
}
constraint c_indata {in_data inside {[-32767:32767]};}
endclass
class seq0 extends uvm_sequence # (item_incode);
`uvm_object_utils (seq0)
function new(string name = "seq0");
super.new(name);
endfunction
virtual task body();
repeat (8) begin
item_incode incode = item_incode::type_id::create("incode");;
start_item (incode);
incode.randomize();
$display("ITEM: %b or %b", incode.in_code, incode.in_data);
`uvm_info("SEQ", $sformatf("Generate new item: %s", incode.convert2str()), UVM_HIGH)
finish_item(incode);
end
`uvm_info("SEQ", $sformatf("Done generation of items"), UVM_LOW)
endtask
endclass