Quantcast
Channel: Cadence Functional Verification Forum
Viewing all articles
Browse latest Browse all 1069

ROM design

$
0
0

I am trying to write verilog code to store 2^36 outputs of C432 benchmark circuit in ROM. It is taking more than 3 days to write all the address, still I haven't completed the code. Can you please guide me whether my approach is correct or not? If not, can you suggest me to shorten the code.


Viewing all articles
Browse latest Browse all 1069

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>