Hi Team,
I set up a very basic mixed signal simulation environment with two inverters (one in sch and the other in verilog). I set up the HED with functional view for the verilog inverter and its working fine.
But when I bind the verilog inverter with a verilog file (using "Specify Reference Verilog") from my local which has a UDP instantiated with in it my simulation failed with the fatal ncelab: *F,CUHUNL.
I understood that since the module view was selected when I referenced my local verilog file, the same has been added to the stop view and that is where it was failing.
Is there any solution to it as I have lots of UDPs and it will be time consuming to write modules for them?
I beg your pardon if I have posted my query in a wrong place.
Thanks and Regards
Susanta