Avoid compiling Verilog/sytemVerilog views every time you netlist (AMS).

Hi,

I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).

The compilation time is extremely long and I only want  to confirm if there is no netlist errors (no simulating).

Thanks.