Hi all,
I am facing a problem when I am trying to simulate verilog code along with analog blocks using the AMS simulator. This is how the story goes:
Initially, with IUS-8.2 installed I was able to simulate simple AMS designs. However, in other AMS designs I was getting an undefined error, which was prompting me to contact Cadence. After searching online, I figured out this had to do with IUS version which was too outdated. Therefore, I asked the sys admin to install INCISIVE-15.20.008. With this package, for the same design I was not able to compile 4 modules from connectLib. For example, for one of the modules I am getting the following error:
ncvlog: *E,NOTSTT (/proj/cad/cadence/incisive-15.20.008.lnx86/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ER_bidir/module/verilog.vams,118|15): expecting a statement [9(IEEE)].
I went back to IUS, by including (softinclude) the appropriate cds.lib file (for IUS) in my cds.lib file. However, when I am trying to simulate the design that I was initially able to simulate with IUS, i.e. before installing INCISIVE, now I get an error displaying:
ncsim: *E,MSSYSTF (/proj/cad/cadence/incisive-15.20.008.lnx86/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2E_2/module/verilog.vams,110|18): User Defined system task or function registered during elaboration and used within the simulation has not been registered during simulation.
It seems that ncsim is trying to compile a module from the INCISIVE installation. Do you have any ideas on how can this be possible?
I double checked that ncsim runs from IUS and not INCISIVE path:
which ncsim
/proj/cad/cadence/ius-8.2.lnx86/tools/bin/ncsim
Let me notice that my configuration is:
IC6.1.5-64b.500.14
MMSIM 13.11
Thank you,
George