Hi to everyone.
I made my circuit in verilogA with the code and circuit part. The simulation is very slow, so I made the systemverilog model.
Now I would compare the results. In some Cadence slide I saw that this is possible:
These are my results:
My question is: Was the image found in the Cadence slide a result of photoshop or is there a function in virtuoso or simvision to compare two results?
If is there this function, how it work?
Thank you very much
L.F.