I am trying to test the VHDL DUT in UVM environment and as i can see using the libverbose all the units are properly resolved when i used irun and it shows error in elaboration as below :
irun: *E,ELBERR: Error during elaboration (status 1), exiting.
I am not able to see any other error messages.
Can you please help me how i can further debug to know the exact reason for the error ?
Image may be NSFW.Clik here to view.
