Hi,
I'm running ams simulation for digital (verilog) and analog (schematic) blocks in a single testbench using hierachy config.
In topcell.vams, I instantiated i_cellA cellA(), and chose cellA as schematic in config file.
The irun.log error is "instance 'i_cellA' of design unit 'cellA' is unresolved in 'worklib.topCell:vams'.".
If I replace schematic view of cellA with an empty(port only) verilogams view, there will be no errors.
Thanks a lot.
icfb 5.10.41.500.6.149
mmsim 13.10.066