Hi,
I am using the Virtuoso Verilog Enviroment (NC-Verilog), in order to generate the functional Verilog model of my top Schematic. For some of the components of my Schematic, I have written their functional models. In the tab Setups -> Netlist, I have selected the option "Single Netlist file". In the generated Netlist, the tools "'include" the modules of the Schematic's components. I want to replace the "`include"s, with the modules inline. How can I achieve this automatically through the tools?
Kind regards,
anm
↧
Replace "`includes" with in-line modules - NC-Verilog
↧
NC-Verilog user manual
Hi,
I am not able to trace the user manual of NC-Verilog. I need it, because I am trying to solve this issue: https://community.cadence.com/cadence_technology_forums/f/functional-verification/39910/replace-includes-with-in-line-modules---nc-verilog
Can anyone point me to an online source of the manual?? Thank you in advance for your feedback.
Kind regards,
anm
↧
↧
Is there a way to change the value of a voltage source (or a generic parameter), "during" the execution of an Interactive mode AMS simulation?
Hello all,
I was wondering if there is a way to change the value of a voltage source interactively, during the execution of an AMS simulation.
In SimVision, I can not deposit a value on a VerilogA model parameter, like DC value or delay.
An example would be how to create the following waverform with user commands:
.
Any help or idea will be very much appreciated.
Many thanks in advance and best regards,
Ardit
↧
xrun timing check
Hi,
I have to perform an RTL simulation using some library cells and some models. Both files have the timing information through specify/specparam definition.
I would like to suppress timing information for the library cells but I want to keep the timing information relative to my models; so I cannot use the -nospecify option during simulation, otherwise all the timing information will be cleaned.
Is it possible to remove the timing information from only some blocks?
I've also tried to precompile the library using -makelib -nospecify options but it doesn't work.
Thanks!
↧
PSpice A/D Stuck in lite version even if I have a license dongle. How to switch ?
I have check lmtools and the license server is functional with the dongle.
OrCAD Capture says that it is full version
Running simulation from there brings up PSpice A/D lite version instead of a licensed version.
In addition there is no simulation results shown.
How do I come out of this loop ?
↧
↧
How to read label inside a particular instance and check its connectivity with the label of another instance
Hi,
I have multiple instance in top cell
Each instance has some labels inside it.
How I can get the instance name and read the labels inside it, and check to which label(of another instance) it is connected.
Thanks
↧
What is the recommended usage : vaelab vs hdlSynthesize?
Hi,
I am going through palladium uxe userguide, which gives user two option to do an rtl/hdl import in ICE mode. User can use either
1) vavlog+vaelab utilities
or
2) hdlImport+hdlSynthesize xel commands to xeCompile
Is there a recommendation to use one over the other? What is the better approach? Why do we have two approaches - what is the latest?
Regards
Ram
↧
Where can I ask tools question on Synopsys VCS simulator?
I mainly used Cadence and it's the best simulator tool out there I know. But I have to do IP support to a customer using VCS.
The tool is really too complex for me to get done some of the most common tasks I do with NCSIM, and they dont seem to have a forum where I can ask questions.
My question is, what are the places people ask questions about their VCS and Verdi tools?
Sorry moderators!
↧
AMS Netlister Error: "Illegal non-local reference to constant function [10.3.5(IEEE)]"
I am simulating corners using ADE XL and the AMS simulator. Netlisting fails with the above error.
The offending line in the netlist is: defparam I15.CORNER = pPar("CORNERVAL");
I15 is a systemverilog model that does NOT contain a parameter named CORNER.
I edited the CDF to remove the component parameter named CORNER, but it keeps reappearing, and causing the same error message.
Thanks in advance for any help.
↧
↧
parametrized cover class instance mapping in vplan
I am using parametrized cover class and I am mapping instance of these cover class with vids defined in vplan.
But every time when I am changing the parameter(sccr_clk_cov#(16, div2)::apb_reg_sccr_clk_en_clr_cg) value , from 16 to 31 , it become red (!)
Could you please suggest me the correct way of mapping.
↧
Fork a task with parameter from within a function
Hi,
Below is what I've tried to start a task with parameter from a function.
function fork_task_in_func()
for (int i = O; i < 3; i++) begin
fork
print_me(i);
join_none
end
endfunction
task print_me(int i);
$display("print me: i: %Od\n", i);
endtaskWhat I expect is as follows,
print me: i: 0
print me: i: 1
print me: i: 2
But the actual outputs are,
print me: i: 3
print me: i: 3
print me: i: 3
Anyone can explain a bit for this result?
Thanks.
↧
How to show connections for a wire?
HI,
For a given wire, I'd like to find the signals connected using that wire.
Is there any way to fulfill that? It's better to use some tcl command to automatically show connections for a bunch of wires.
Thanks.
↧
SDF back annotation in systemVerilog design using interfaces
I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the modules. here is part of the code:
module topmodule(
intf1 clk,inp1,inp2,outp);
intf1 out();
// Instance the interface with an input, using named connection
RC DUT(clk, inp1, inp2, out);
and here is part of interface definition,
interface intf1;
logic data=0;and I have two task and function in my interface. I write a SDF file but modelsim said 'failed to find port '/tbench_top/clk/data' and 'failed to find port '/tbench_top/DUT/inp1/data'. It means it didn't recognize the 'data' port which is defined within the interface. here is part of my SDF file,
INTERCONNECT clk.data DUT.inp1.data (.145::.145) (.125::.125))So, how must I write SDF when I use interfaces? Thanks for any help.
↧
↧
How to show posedges by Simvision expression?
Hi,
In Simvision, users can easily view conditional combination of some signals by its expression feature.
However, if I want to view conditions like,
@posedge(A) & (B == 'h1234)
How can I achieve this by Simvision expression?
Thanks.
↧
DLCSMD Errors
Hi,
I'm getting the following compile error:
xmvlog: *E,DLCSMD: Dependent checksum verilog_package work.foo_pkg:sv (VST) doesn't match with the checksum that's in the header of: verilog_package work.foo_bar_pkg:sv (VST).
import foo_bar_pkg::*;
This is starting from a completely clean build. (Historic posts on this error have talked about removing INCA_libs as the solution).
Other than that I can't see what we could be doing here to cause this error. Any suggestions would be greatly received.
Kind Regards
↧
What could be the reason of *E,DLCSMD error?
Hi,
I ran into an error like,
*E,DLCSMD Dependent checksum module A.B:module (VST) doesn't match with the checksum that's in the header of: snapshot worklib.top_dut:sv (SSS).
*F, NOSIMU: Errors initializating simulation 'top_dut'.
Any one can suggest on this?
Thanks.
↧
What's the definition and the function of value()
Hi, all
I'm new to specman E, and begin learning it by reading Design Verification with E. I've many times the utilization of function value, such as:
keep tx_monitor.file_logger.to_file == value(tx_log_filename);
keep tx_bfm.driver == value(tx_driver);
Could anyone explain me about the utilization of value().
Many thanks!
Tao
↧
↧
Puzzled by definition of this struct
Hi, all
me again, I've read a definition of struct as follows:
-- Definition of the packet struct
struct packet {
kind : [good,bad];
addr : uint (bits : 2) ;
len : uint (bits : 6) ;
data [len] : list of byte ;
!parity : byte ;
}; |
Here, is kind a enumerated type, as it may already be defined?
Tao
↧
How do I exclude my CPU netlist from probe?
Hi all,
I use the following statement to probe all the hierarchy in my testbench. However I wish to exclude the CPU netlist model in tb.design.hier2.CPU_netlist.
How do I do that?
"database -open ncsim.vcd -vcd
probe -all -depth all"
↧
black-boxing using "-bbox" in Jasper
Hi,
In Japser there is a provision for black-boxing., What is the difference between:
a. black-boxing during compile/analyze
b. black-boxing during elaboration.
-Thanks
↧