Running SVA for a VHDL design (binding method)

My design is in VHDL so, my top file is ../VHDL/top.vhd
As it is now, the testbenches simulation do run fine. These are written in (System)Verilog.

How can I use the approach of SVA binding, to run an assertion file for a specific subcomponent on which I am interested in?!?
The component is comp1.vhd
The SystemVerilog Assertions (SVA) file for this component is comp1_sva.sv

I also have created the comp1_bind.txt, the binding file
with the generic structure inside

bind (design_module_name/design_instance_name) {sva_module_name}{bind_instance_name}(port_list);

The goal is to execute something like

xrun -assert -extbind comp1_bind.txt comp1.vhd comp1_sva.sv

Questions:
1. is the approach correct, in order to test a VHDL-design using SystemVerilog Assertions?
2. how to write exactly the comp1_bind.txt


NOTE: using above all the commands and guidance as found in the Xcelium help/tutorials/example files in the paths
<xcelium_install_dir>/doc/abvquickstart/...
<xcelium_install_dir>/doc/abvsimulate/...

NOTE2: for now, I only want to run this simulation (or testbench, whatever the naming is) for this component only, not the whole design.

Thanks for any advice!