Quantcast
Channel: Cadence Functional Verification Forum
Viewing all articles
Browse latest Browse all 1074

How to avoid rounding during a force of a real variable

$
0
0

Hi,

I'm trying to force a real variable in ADC model with 6 digits after decimal point. However what I can see that sometimes variable is rounded on 5 digits, and sometimes it isn't. I can find any pattern when it's rounded. In the following screenshot I connected by red lines values where rounded doesn't happen. Yellow and green lines mark that rounding happen.

I have few ADC instances, with two channels (odd and even). Every cannel has 2 inputs - a and b input.

So, Is there any way to debug this issue? Why sometimes rounding happens and sometimes it doesn't?

xcelium_18.09.009

Forcing mechanism - $xm_force(forced_path, $sformatf("%0f", adc_input_voltage_real));

Thanks,

Marko


Viewing all articles
Browse latest Browse all 1074

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>