VCS to IRUN Conversion Error, UVM-1.1 System Verilog

Hi,

   I am using INCISIV 11.1 to compile a project which works perfectly on VCS, However I get the following errors on cadence using the irun command .

ncvlog: *E, CLSSLV Class reference illegal in this reference on line :

 data_in[0] <= link_if.cbd.link_tx_serdes_data_0

and ncvlog: *E, DYNNBA Reference to whole or element of dynamic array/fixed array of dynamic array are illegal in this context

data_in is declared as a protected logic [`OSI_WD_WIDTH-1:0] data_in [ ] and initialized to size 16.  link_tx_serdes_data_0 is declared as logic [`OSI_SERDES_WIDTH-1:0] in an interface. link_tx_serdes_data_0 is declared as an input in clocking block cbd.

The data_in is also registered as a uvm_component:

.....

`uvm_field_array_int(data_in,UVM_ALL_ON)

All required files have been compiled prior to compiling this file. And the whole project works perfectly on VCS. 

Maisum.