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Is it possible to create a register block that contain multiple register maps...
Hi, I'm considering moving to reg_verifier for register model generation. However, I'm having trouble to create multiple address maps for the same hardware registers.I want to generate a model with...
View ArticleI'm using RHEL 8.10, and XCELIUM MAIN version 23.09_013 isn't working properly.
I'm using RHEL 8.10, and XCELIUM MAIN version 23.09_013 isn't working properly. Is there a problem with the OS? The log is as...
View ArticleThe bloackbox option "-jg_bbmod" does not work
Dear all, Does anyone knows how to successfully do blackboxing on certain modules when running JasperGold UNR? The blackbox option in Product Version 2024.09 is -jg_bbmod, and I passed it to the...
View ArticleGetting coveritems from Jaspergold
Hello, I was wondering if there is a way to report the coveritems generated from coverage measurement in Jaspergold? Maybe something similar to reporting the coverage data as txt or html file?
View ArticleXMSIM: *E,SST2ER: SST2 interface error: Stale file handle
Hi, I am facing below issue in regression. xmsim: *E,SST2ER: SST2 interface error: Stale file handle. Rahul suggested to refer the cadence site and I picked up the first solution (simulation...
View ArticleMissing symbols in a ucis library
Hi dear all, I was trying to use cocotb and the pyvsc python based verification library with xcelium versions 23.03 24.03 and 25.03 but trying touse the libucis.so shared library provided by cadence...
View ArticleHow to initiate the secure/non-secure transfers from cadence AHB5 VIP.
How to initiate the secure/non-secure transfers from cadence AHB5 VIP. Also please provide the necessary configuration and transaction item details.Please provide us the pseudo code for various INCR...
View ArticleTestable and testconstraint attribute supports in reg_verifier?
Hi,I have added testable and testconstraint attributes to IP-XACT XML. While converting XML to RAL model using reg_verifier tool those attributes ignored and genrated RAL model does not contain these...
View ArticleCode coverage syntax for scripting tcl exclusion file
Where can I found the syntax for scripting a tcl file for exclusion on coverage when using xceliumI have a sample , but what is the syntax to write my own ecxlusion conditions exclude -covered -inst...
View ArticleExclusion of Signals Across Hierarchy for Toggle Coverage using CCF File
We are currently working on excluding specific signals from toggle coverage in the top-level module using the exclude.list file in the CCF. The exclusion is applied using the following regular...
View ArticleWant to run Vmanager in batch mode
How to check the status of a regression test after launching it in batch modeWe used the following cmds to trigger a regression test:export VMGR_PROJECT=xxxxxx vmanager -batch -init run.tcl The run.tcl...
View ArticleCan I change *.ucd type of file into .json to add svseed, coverpoints
Hi,Can I get the details of covergroup details like coverpoint, no of bins, score and test svseed from .ucd into .json format?
View Articlevmanager: custom result evaluation
Hi all,I would like to implement a "custom result evaluation" that can influence the test status reported in the dashboard in vmanager. What I have in mind isopen a sim result fileperform some...
View ArticleHow to eliminate DLCSMD errors in Xcelium's xrun
Hello,I am using cocotb in python to simulate SystemVerilog files and while there is no issue with other simulators such as modelsim, I came accross DLCSMD error in xrun. I have looked previous similar...
View ArticleFunctional Coverage at SOC or Sub System Level
Hi All,At subsystem or SOC verification level,let’s say there are three IPs integrated : IP1, IP2 and IP3.Individually from block level verification, all IPs functional coverage is achieved 100%.IP1 FC...
View ArticleSimple Assertion for Counter
Hi all, Question_1 : Assertion requirement : When Enable is HIGH, counter should be increment to previous clock cycle value, when Enable is LOW, counter should keep same value as previous cycle. Below...
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SimVision: how to find all signals in the database matching a specific pattern?
Let's imagine I have a signal in my waveform database like test.top.channel_0.subChannel_A.mySignal.My design has many identical channels and each channel has many identical sub-channels, so the...
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The simulation finished - Interactive session ending soon
Hello Everyone,I am trying to run my mixed signal testbench using cadence xcelium. When I try to open the terminal interactively, it says - 'This simulation finished ...'Please find below...
View ArticleI observe following error when running xrun -sv
Design hierarchy summary: Instances Unique Modules: 2 2 Verilog packages: 0 1 Registers: 15 15 Scalar wires: 12 - Always blocks: 2 2 Initial blocks: 4 4 Pseudo assignments: 4 - Simulation timescale:...
View ArticlePass variables to tcl script in Xcelium
Hello,I'm trying to pass a Variable through a command line input in the environment, so that my tcl script can take this for its startup initialization.xrun ... -command_that_sets_sets_a_variable...
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